Home
last modified time | relevance | path

Searched refs:PLL_CPLL (Results 1 – 25 of 40) sorted by relevance

12

/linux-6.15/include/dt-bindings/clock/
H A Drk3188-cru-common.h13 #define PLL_CPLL 3 macro
H A Drk3128-cru.h13 #define PLL_CPLL 3 macro
H A Drk3228-cru.h13 #define PLL_CPLL 3 macro
H A Drockchip,rk3562-cru.h18 #define PLL_CPLL 5 macro
H A Drk3328-cru.h13 #define PLL_CPLL 3 macro
H A Drk3288-cru.h13 #define PLL_CPLL 3 macro
H A Drk3368-cru.h13 #define PLL_CPLL 4 macro
H A Dpx30-cru.h9 #define PLL_CPLL 3 macro
H A Drockchip,rk3528-cru.h13 #define PLL_CPLL 1 macro
H A Drockchip,rk3576-cru.h20 #define PLL_CPLL 4 macro
H A Drockchip,rv1126-cru.h67 #define PLL_CPLL 3 macro
H A Drk3399-cru.h14 #define PLL_CPLL 4 macro
H A Drockchip,rk3588-cru.h20 #define PLL_CPLL 5 macro
H A Drk3568-cru.h72 #define PLL_CPLL 3 macro
/linux-6.15/drivers/clk/rockchip/
H A Dclk-rk3188.c220 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
231 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
H A Dclk-rk3128.c163 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
H A Dclk-rk3228.c173 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
H A Dclk-rk3328.c221 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
H A Dclk-rk3368.c136 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
/linux-6.15/arch/arm64/boot/dts/rockchip/
H A Drk3368-r88.dts216 assigned-clock-parents = <&cru PLL_CPLL>;
H A Drk3368-lba3368.dts558 assigned-clock-parents = <&cru PLL_CPLL>;
H A Drk3528.dtsi329 <&cru PLL_PPLL>, <&cru PLL_CPLL>,
H A Drk3399-gru-scarlet.dtsi368 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
/linux-6.15/arch/arm/boot/dts/rockchip/
H A Drk3188-bqedison2qc.dts227 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
H A Drk3066a.dtsi232 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,

12