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Searched refs:PLL0 (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/sound/soc/codecs/
H A Dak4642.c116 #define PLL0 (1 << 4) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dmicrochip,mpfs-ccc.yaml24 - description: PLL0's control registers
35 - description: PLL0's refclk0
36 - description: PLL0's refclk1
H A Dstarfive,jh7110-syscrg.yaml30 - description: PLL0
44 - description: PLL0
H A Dsilabs,si5351.yaml216 /* Use XTAL input as source of PLL0 and PLL1 */
225 * - PLL0 as clock source of multisynth 0
227 * - Multisynth 0 can change PLL0
/linux-6.15/drivers/media/dvb-frontends/
H A Dzl10039.c39 PLL0 = 0, enumerator
218 ret = zl10039_write(state, PLL0, buf, sizeof(buf)); in zl10039_set_params()
/linux-6.15/Documentation/devicetree/bindings/phy/
H A Dphy-cadence-torrent.yaml39 PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
42 Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.
/linux-6.15/include/dt-bindings/clock/
H A Dqcom,gcc-msm8660.h256 #define PLL0 247 macro
H A Dqcom,gcc-ipq806x.h229 #define PLL0 220 macro
H A Dqcom,gcc-mdm9615.h286 #define PLL0 276 macro
H A Dqcom,gcc-msm8960.h284 #define PLL0 276 macro
/linux-6.15/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
/linux-6.15/Documentation/devicetree/bindings/clock/st/
H A Dst,flexgen.txt21 | | |PLL0 | | | | |Dividers| |Dividers| | |
/linux-6.15/arch/mips/boot/dts/ingenic/
H A Dgcw0.dts443 * PLL0 frequency on demand without having to suspend peripherals.
446 * Put the GPU under PLL0 since we want a higher frequency.
/linux-6.15/drivers/clk/qcom/
H A Dgcc-mdm9615.c1615 [PLL0] = &pll0.clkr,
H A Dgcc-ipq806x.c3067 [PLL0] = &pll0.clkr,