| /linux-6.15/Documentation/translations/zh_CN/arch/loongarch/ |
| H A D | irq-chip-model.rst | 19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
46 | PCH-PIC | | PCH-MSI |
63 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
77 | PCH-PIC | | PCH-MSI |
94 CPU串口 (UARTs) 中断发送到PCH-PIC, 而其他所有设备的中断则分别发送到所连接的PCH_PIC/
108 | PCH-PIC | | PCH-MSI |
150 送达CPUINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/PCH-LPC，然后由EIOINTC
164 | PCH-PIC | | PCH-MSI |
204 PCH-PIC::
[all …]
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| /linux-6.15/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | open-pic.txt | 1 * Open PIC Binding
4 representation of an Open PIC compliant interrupt controller. This binding is
5 based on the binding defined for Open PIC in [1] and is a superset of that
13 - compatible: Specifies the compatibility list for the PIC. The type
20 as an Open PIC. No property value shall be defined.
31 - pic-no-reset: The presence of this property indicates that the PIC
55 * An Open PIC interrupt controller
62 // this Open PIC node do not need a parent address specifier.
71 // Compatible with Open PIC.
74 // The PIC shall not be reset.
[all …]
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| H A D | marvell,armada-8k-pic.txt | 1 Marvell Armada 7K/8K PIC Interrupt controller
4 This is the Device Tree binding for the PIC, a secondary interrupt
13 - reg: the register area for the PIC interrupt controller
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| H A D | intel,ce4100-lapic.yaml | 46 PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
50 For OF based systems, it is by default set to PIC mode.
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| H A D | loongson,pch-pic.yaml | 7 title: Loongson PCH PIC Controller
27 to PCH PIC.
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| H A D | cdns,xtensa-mx.txt | 6 Remaining properties have exact same meaning as in Xtensa PIC
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| H A D | google,goldfish-pic.txt | 1 Android Goldfish PIC
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| H A D | loongson,htpic.yaml | 17 interrupts from PCH PIC connected on HyperTransport bus.
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| /linux-6.15/Documentation/translations/zh_TW/arch/loongarch/ |
| H A D | irq-chip-model.rst | 15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片組的主中
19 全局中斷控制器（每個芯片一個，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
27 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
46 | PCH-PIC | | PCH-MSI |
63 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
77 | PCH-PIC | | PCH-MSI |
117 PCH-PIC::
156 - PCH-PIC/PCH-MSI：即《龍芯7A1000橋片用戶手冊》第5章所描述的“中斷控制器”；
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| /linux-6.15/arch/powerpc/boot/dts/ |
| H A D | ep8248e.dts | 72 interrupt-parent = <&PIC>;
77 interrupt-parent = <&PIC>;
135 interrupt-parent = <&PIC>;
148 interrupt-parent = <&PIC>;
161 interrupt-parent = <&PIC>;
174 interrupt-parent = <&PIC>;
186 interrupt-parent = <&PIC>;
192 PIC: interrupt-controller@10c00 { label
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| H A D | mgcoge.dts | 140 interrupt-parent = <&PIC>;
153 interrupt-parent = <&PIC>;
164 interrupt-parent = <&PIC>;
194 interrupt-parent = <&PIC>;
207 interrupt-parent = <&PIC>;
218 interrupt-parent = <&PIC>;
226 interrupt-parent = <&PIC>;
246 PIC: interrupt-controller@10c00 { label
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| H A D | mpc885ads.dts | 32 interrupt-parent = <&PIC>;
103 interrupt-parent = <&PIC>;
115 interrupt-parent = <&PIC>;
120 PIC: interrupt-controller@0 { label
134 interrupt-parent = <&PIC>;
171 interrupt-parent = <&PIC>;
228 interrupt-parent = <&PIC>;
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| H A D | tqm8xx.dts | 39 interrupt-parent = <&PIC>;
73 interrupt-parent = <&PIC>;
85 interrupt-parent = <&PIC>;
115 interrupt-parent = <&PIC>;
120 PIC: pic@0 { label
161 interrupt-parent = <&PIC>;
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| H A D | ep88xc.dts | 32 interrupt-parent = <&PIC>;
98 interrupt-parent = <&PIC>;
110 interrupt-parent = <&PIC>;
115 PIC: interrupt-controller@0 { label
129 interrupt-parent = <&PIC>;
165 interrupt-parent = <&PIC>;
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| H A D | adder875-redboot.dts | 37 interrupt-parent = <&PIC>;
100 interrupt-parent = <&PIC>;
112 interrupt-parent = <&PIC>;
117 PIC: interrupt-controller@0 { label
156 interrupt-parent = <&PIC>;
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| H A D | adder875-uboot.dts | 37 interrupt-parent = <&PIC>;
99 interrupt-parent = <&PIC>;
111 interrupt-parent = <&PIC>;
116 PIC: interrupt-controller@0 { label
155 interrupt-parent = <&PIC>;
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| H A D | mpc866ads.dts | 32 interrupt-parent = <&PIC>;
83 interrupt-parent = <&PIC>;
88 PIC: pic@0 { label
129 interrupt-parent = <&PIC>;
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| H A D | gamecube.dts | 50 interrupt-parent = <&PIC>;
62 PIC: pic { label
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| /linux-6.15/Documentation/arch/loongarch/ |
| H A D | irq-chip-model.rst | 11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
43 | PCH-PIC | | PCH-MSI |
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
75 | PCH-PIC | | PCH-MSI |
92 go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other
93 devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual
107 | PCH-PIC | | PCH-MSI |
171 | PCH-PIC | | PCH-MSI |
211 PCH-PIC::
[all …]
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| /linux-6.15/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/ |
| H A D | usb.txt | 13 interrupt-parent = <&PIC>;
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| /linux-6.15/Documentation/arch/x86/i386/ |
| H A D | IO-APIC.rst | 30 2: 0 XT-PIC cascade
31 13: 1 XT-PIC fpu
39 Some interrupts are still listed as 'XT PIC', but this is not a problem;
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| /linux-6.15/Documentation/devicetree/bindings/usb/ |
| H A D | maxim,max3421.txt | 21 interrupt-parent = <&PIC>;
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| /linux-6.15/arch/openrisc/boot/dts/ |
| H A D | or1ksim.dts | 34 * OR1K PIC is built into CPU and accessed via special purpose
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| H A D | simple_smp.dts | 46 * OR1K PIC is built into CPU and accessed via special purpose
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| /linux-6.15/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| H A D | serial.txt | 27 interrupt-parent = <&PIC>;
|