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Searched refs:PA_CL_UCP_2_W__DATA_REGISTER_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h5686 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffffL macro
H A Dgfx_7_2_sh_mask.h5633 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff macro
H A Dgfx_8_0_sh_mask.h6421 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff macro
H A Dgfx_8_1_sh_mask.h6955 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h15497 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK … macro
H A Dgc_9_1_sh_mask.h16802 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK … macro
H A Dgc_9_2_1_sh_mask.h16674 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK … macro
H A Dgc_9_4_3_sh_mask.h18975 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK … macro
H A Dgc_9_4_2_sh_mask.h8923 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK … macro
H A Dgc_11_5_0_sh_mask.h16560 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK … macro
H A Dgc_11_0_0_sh_mask.h20591 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK … macro
H A Dgc_12_0_0_sh_mask.h28264 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK … macro
H A Dgc_10_1_0_sh_mask.h22995 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK … macro
H A Dgc_11_0_3_sh_mask.h22921 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK … macro
H A Dgc_10_3_0_sh_mask.h21103 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK … macro