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Searched refs:NumDispClkLevelsEnabled (Results 1 – 16 of 16) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.h117 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
144 uint8_t NumDispClkLevelsEnabled; // Applies to both Dispclk and Dppclk member
H A Ddcn35_clk_mgr.c936 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn35_clk_mgr_helper_populate_bw_params()
937 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn35_clk_mgr_helper_populate_bw_params()
939 clock_table->NumDispClkLevelsEnabled); in dcn35_clk_mgr_helper_populate_bw_params()
941 clock_table->NumDispClkLevelsEnabled); in dcn35_clk_mgr_helper_populate_bw_params()
1016 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
1017 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
1230 smu_dpm_clks_b->dpm_clks->NumDispClkLevelsEnabled = in translate_to_DpmClocks_t_dcn35()
1231 smu_dpm_clks_a->dpm_clks->NumDispClkLevelsEnabled; in translate_to_DpmClocks_t_dcn35()
1348 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn35_clk_mgr_construct()
1360 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn35_clk_mgr_construct()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu14_driver_if_v14_0_0.h134 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
165 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
H A Dsmu13_driver_if_v13_0_5.h120 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
H A Dsmu13_driver_if_yellow_carp.h132 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
H A Dsmu13_driver_if_v13_0_4.h133 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
H A Dsmu11_driver_if_vangogh.h145 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c587 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn31_clk_mgr_helper_populate_bw_params()
588 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn31_clk_mgr_helper_populate_bw_params()
589 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()
590 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()
758 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn31_clk_mgr_construct()
769 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn31_clk_mgr_construct()
H A Ddcn31_smu.h141 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c639 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn314_clk_mgr_helper_populate_bw_params()
640 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn314_clk_mgr_helper_populate_bw_params()
641 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()
642 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()
867 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn314_clk_mgr_construct()
878 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn314_clk_mgr_construct()
H A Ddcn314_smu.h60 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c514 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn316_clk_mgr_helper_populate_bw_params()
515 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn316_clk_mgr_helper_populate_bw_params()
516 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn316_clk_mgr_helper_populate_bw_params()
517 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn316_clk_mgr_helper_populate_bw_params()
H A Ddcn316_smu.h87 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h79 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
H A Ddcn315_clk_mgr.c534 …table.entries[i-1].dispclk_mhz = clock_table->DispClocks[clock_table->NumDispClkLevelsEnabled - 1]; in dcn315_clk_mgr_helper_populate_bw_params()
535 …k_table.entries[i-1].dppclk_mhz = clock_table->DppClocks[clock_table->NumDispClkLevelsEnabled - 1]; in dcn315_clk_mgr_helper_populate_bw_params()
685 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn315_clk_mgr_construct()
696 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn315_clk_mgr_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h116 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member