Home
last modified time | relevance | path

Searched refs:MDIO_MMD_PCS (Results 1 – 25 of 41) sorted by relevance

12

/linux-6.15/drivers/net/phy/
H A Dmarvell-88q2xxx.c133 { MDIO_MMD_PCS, 0xffe4, 0x07b5 },
153 { MDIO_MMD_PCS, 0xfe1b, 0x48 },
154 { MDIO_MMD_PCS, 0xffe4, 0x6b6 },
160 { MDIO_MMD_PCS, 0xfe79, 0x0 },
166 { MDIO_MMD_PCS, 0xfbba, 0xcb2 },
167 { MDIO_MMD_PCS, 0xfbbb, 0xc4a },
172 { MDIO_MMD_PCS, 0xfe1b, 0x58 },
173 { MDIO_MMD_PCS, 0xfe79, 0x4 },
174 { MDIO_MMD_PCS, 0xfe5f, 0xe8 },
202 { MDIO_MMD_PCS, 0xfe1b, 0x58 },
[all …]
H A Dbcm87xx.c114 pcs_status = phy_read_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_read_status()
144 reg = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_CONTROL); in bcm87xx_config_intr()
150 err = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_STATUS); in bcm87xx_config_intr()
155 err = phy_write_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_config_intr()
159 err = phy_write_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_config_intr()
164 err = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_STATUS); in bcm87xx_config_intr()
H A Dmarvell-88x2222.c90 int ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL, in mv2222_disable_aneg()
100 int ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL, in mv2222_enable_aneg()
119 return phy_modify_mmd(phydev, MDIO_MMD_PCS, in mv2222_set_sgmii_speed()
130 return phy_modify_mmd(phydev, MDIO_MMD_PCS, in mv2222_set_sgmii_speed()
140 return phy_modify_mmd(phydev, MDIO_MMD_PCS, in mv2222_set_sgmii_speed()
292 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_ADVERTISE, in mv2222_config_aneg()
307 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1); in mv2222_aneg_done()
315 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_STAT); in mv2222_aneg_done()
328 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1); in mv2222_read_status_10g()
364 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_STAT); in mv2222_read_status_1g()
[all …]
H A Dsmsc.c280 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR, in lan874x_phy_config_init()
286 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_MCFGR, in lan874x_phy_config_init()
304 rc = phy_read_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR); in lan874x_get_wol()
376 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, in lan874x_set_wol_pattern()
382 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, in lan874x_set_wol_pattern()
390 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, *mask); in lan874x_set_wol_pattern()
400 phy_write_mmd(phydev, MDIO_MMD_PCS, reg, 0); in lan874x_set_wol_pattern()
424 rc = phy_read_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR); in lan874x_set_wol()
486 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, in lan874x_set_wol()
493 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR, in lan874x_set_wol()
H A Dmarvell10g.c200 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP); in mv2110_hwmon_read_temp_reg()
337 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, in mv3310_reset()
342 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, in mv3310_reset()
356 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1); in mv3310_get_downshift()
379 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, in mv3310_set_downshift()
398 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2, in mv3310_set_downshift()
408 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, in mv3310_set_downshift()
417 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1); in mv3310_get_edpd()
1028 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1); in mv3310_read_status_copper()
1257 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO); in mv3310_get_number_of_ports()
[all …]
H A Dadin1100.c224 return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL, in adin_set_loopback()
228 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL, in adin_set_loopback()
H A Dmicrochip.c290 val = phy_read_mmd(phydev, MDIO_MMD_PCS, in lan88xx_config_init()
294 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG, in lan88xx_config_init()
H A Dadin.c203 { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG },
206 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
207 { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG },
/linux-6.15/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v1.c322 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_pcs_power_cycle()
325 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_pcs_power_cycle()
330 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_pcs_power_cycle()
373 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); in xgbe_phy_kr_mode()
376 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); in xgbe_phy_kr_mode()
378 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_kr_mode()
381 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_kr_mode()
416 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); in xgbe_phy_kx_2500_mode()
419 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); in xgbe_phy_kx_2500_mode()
421 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_kx_2500_mode()
[all …]
H A Dxgbe-mdio.c164 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); in xgbe_an37_disable_interrupts()
166 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); in xgbe_an37_disable_interrupts()
173 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); in xgbe_an37_enable_interrupts()
175 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); in xgbe_an37_enable_interrupts()
1557 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); in xgbe_dump_phy_registers()
1559 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); in xgbe_dump_phy_registers()
1561 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); in xgbe_dump_phy_registers()
1563 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); in xgbe_dump_phy_registers()
1565 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); in xgbe_dump_phy_registers()
1567 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); in xgbe_dump_phy_registers()
[all …]
H A Dxgbe-platform.c498 pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_platform_suspend()
500 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); in xgbe_platform_suspend()
516 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); in xgbe_platform_resume()
H A Dxgbe-pci.c446 pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_pci_suspend()
448 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); in xgbe_pci_suspend()
462 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); in xgbe_pci_resume()
/linux-6.15/drivers/net/phy/qcom/
H A Dqca808x.c117 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, in qca808x_phy_fast_retrain_config()
119 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, in qca808x_phy_fast_retrain_config()
121 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, in qca808x_phy_fast_retrain_config()
123 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, in qca808x_phy_fast_retrain_config()
218 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in qca808x_config_init()
348 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); in qca808x_cable_test_start()
349 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); in qca808x_cable_test_start()
350 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); in qca808x_cable_test_start()
351 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); in qca808x_cable_test_start()
352 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); in qca808x_cable_test_start()
[all …]
H A Dat803x.c371 return phy_modify_mmd(phydev, MDIO_MMD_PCS, in at803x_smarteee_config()
386 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, in at803x_smarteee_config()
391 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, in at803x_smarteee_config()
840 return phy_modify_mmd(phydev, MDIO_MMD_PCS, in at8031_probe()
881 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, in at8031_set_wol()
886 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, in at8031_set_wol()
H A Dqca83xx.c57 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); in qca83xx_get_stat()
113 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); in qca83xx_config_init()
H A Dqcom-phy-lib.c83 phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], in at803x_set_wol()
536 val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); in qca808x_cdt_fault_length()
598 val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); in qca808x_cable_test_get_status()
/linux-6.15/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88x201x.c46 cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8304, 0xdddd); in led_init()
214 cphy_mdio_read(cphy, MDIO_MMD_PCS, 0x8300, &val); in mv88x201x_phy_create()
215 cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8300, val | 1); in mv88x201x_phy_create()
219 cphy_mdio_read(cphy, MDIO_MMD_PCS, MDIO_STAT2, &val); in mv88x201x_phy_create()
/linux-6.15/drivers/vfio/platform/reset/
H A Dvfio_platform_amdxgbe.c69 pcs_value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1); in vfio_platform_amdxgbe_reset()
71 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1, pcs_value); in vfio_platform_amdxgbe_reset()
76 pcs_value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_PCS, in vfio_platform_amdxgbe_reset()
/linux-6.15/drivers/net/pcs/
H A Dpcs-xpcs-wx.c152 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_CTRL2); in txgbe_xpcs_mode_quirk()
185 xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBR); in txgbe_xpcs_switch_mode()
190 xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBX); in txgbe_xpcs_switch_mode()
192 xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL1, 0); in txgbe_xpcs_switch_mode()
H A Dpcs-xpcs.c208 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); in xpcs_read_vpcs()
213 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); in xpcs_write_vpcs()
218 return xpcs_modify_vendor(xpcs, MDIO_MMD_PCS, reg, mask, val); in xpcs_modify_vpcs()
242 dev = MDIO_MMD_PCS; in xpcs_soft_reset()
277 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2); in xpcs_read_fault_c73()
286 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS); in xpcs_read_fault_c73()
295 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); in xpcs_read_fault_c73()
302 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2); in xpcs_read_fault_c73()
894 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); in xpcs_get_state_c73()
1248 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); in xpcs_read_ids()
[all …]
/linux-6.15/drivers/net/ethernet/sfc/falcon/
H A Dtxc43128_phy.c212 ctrl = ef4_mdio_read(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL); in txc_bist_one()
214 ef4_mdio_write(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL, ctrl); in txc_bist_one()
265 ef4_mdio_write(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL, ctrl); in txc_bist_one()
272 return txc_bist_one(efx, MDIO_MMD_PCS, TXC_BIST_CTRL_TYPE_TSD); in txc_bist()
403 txc_glrgs_lane_power(efx, MDIO_MMD_PCS); in txc_set_power()
436 txc_reset_logic_mmd(efx, MDIO_MMD_PCS); in txc_reset_logic()
H A Dqt202x_phy.c81 reg = ef4_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG); in qt2025c_wait_heartbeat()
112 reg = ef4_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG); in qt2025c_wait_fw_status_good()
167 firmware_id[i] = ef4_mdio_read(efx, MDIO_MMD_PCS, in qt2025c_firmware_id()
464 mmd = MDIO_MMD_PCS; in qt202x_phy_get_module_eeprom()
/linux-6.15/include/uapi/linux/
H A Dmdio.h21 #define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */ macro
154 #define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
/linux-6.15/rust/kernel/net/phy/
H A Dreg.rs147 pub const PCS: Self = Mmd(uapi::MDIO_MMD_PCS as u8);
/linux-6.15/drivers/net/phy/realtek/
H A Drealtek_main.c770 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) in rtlgen_read_mmd()
804 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) in rtl822x_read_mmd()
1111 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); in rtlgen_supports_mmd()
1113 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); in rtlgen_supports_mmd()

12