Searched refs:IMX6UL_CLK_PLL2_BUS (Results 1 – 3 of 3) sorted by relevance
35 #define IMX6UL_CLK_PLL2_BUS 26 macro
189 hws[IMX6UL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); in imx6ul_clocks_init()516 clk_set_parent(hws[IMX6UL_CLK_PERIPH_PRE]->clk, hws[IMX6UL_CLK_PLL2_BUS]->clk); in imx6ul_clocks_init()
80 <&clks IMX6UL_CLK_PLL2_BUS>,