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Searched refs:DP_RECEIVER_CAP_SIZE (Results 1 – 25 of 32) sorted by relevance

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/linux-6.15/include/drm/display/
H A Ddrm_dp_helper.h53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
140 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate() argument
194 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_is_branch() argument
561 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
579 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
602 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
606 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
620 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
625 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
[all …]
H A Ddrm_dp_mst_helper.h738 u8 dpcd[DP_RECEIVER_CAP_SIZE];
855 enum drm_dp_mst_mode drm_dp_read_mst_cap(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE…
H A Ddrm_dp.h1671 #define DP_RECEIVER_CAP_SIZE 0xf macro
/linux-6.15/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c327 if (offset < DP_RECEIVER_CAP_SIZE) { in __read_delay()
376 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay() argument
400 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_channel_eq_delay() argument
1101 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_extended_dpcd_caps() argument
1103 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; in drm_dp_read_extended_dpcd_caps()
1155 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_dpcd_caps() argument
1189 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_downstream_info() argument
1521 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_mode() argument
1587 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_debug() argument
1757 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_sink_count_cap() argument
[all …]
/linux-6.15/drivers/gpu/drm/hisilicon/hibmc/dp/
H A Ddp_comm.h40 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.h16 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);
H A Dintel_dp_link_training.c77 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in intel_dp_read_lttpr_phy_caps() argument
93 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_lttpr_common_caps() argument
144 static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_init_lttpr_phys() argument
194 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_init_lttpr() argument
209 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_dprx_caps() argument
260 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in intel_dp_init_lttpr_and_dprx_caps()
H A Dintel_dp_tunnel.c302 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in intel_dp_tunnel_resume()
H A Dintel_dp_mst.c1671 u8 dpcd_caps[DP_RECEIVER_CAP_SIZE]; in intel_dp_mst_read_decompression_port_dsc_caps()
1687 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in detect_dsc_hblank_expansion_quirk()
/linux-6.15/drivers/gpu/drm/msm/dp/
H A Ddp_panel.h31 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.15/drivers/gpu/drm/rockchip/
H A Dcdn-dp-core.h103 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.15/drivers/gpu/drm/nouveau/
H A Dnouveau_encoder.h85 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Datombios_dp.c42 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
495 u8 dpcd[DP_RECEIVER_CAP_SIZE];
753 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in amdgpu_atombios_dp_link_train()
H A Damdgpu_mode.h554 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.15/drivers/gpu/drm/nouveau/include/nvif/
H A Doutp.h107 int nvif_outp_dp_train(struct nvif_outp *, u8 dpcd[DP_RECEIVER_CAP_SIZE],
H A Dif0012.h243 __u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Doutp.h48 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.15/drivers/gpu/drm/radeon/
H A Datombios_dp.c37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
540 u8 dpcd[DP_RECEIVER_CAP_SIZE];
836 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in radeon_dp_link_train()
H A Dradeon_mode.h469 u8 dpcd[DP_RECEIVER_CAP_SIZE];
/linux-6.15/drivers/gpu/drm/bridge/analogix/
H A Danalogix-anx6345.c63 u8 dpcd[DP_RECEIVER_CAP_SIZE];
134 &anx6345->dpcd, DP_RECEIVER_CAP_SIZE); in anx6345_dp_link_training()
H A Danalogix-anx78xx.c83 u8 dpcd[DP_RECEIVER_CAP_SIZE];
647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); in anx78xx_dp_link_training()
/linux-6.15/drivers/gpu/drm/tegra/
H A Ddp.c172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value; in drm_dp_link_probe()
/linux-6.15/drivers/gpu/drm/nouveau/nvif/
H A Doutp.c113 nvif_outp_dp_train(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 lttprs, in nvif_outp_dp_train() argument
/linux-6.15/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c1401 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in cdns_mhdp_fill_sink_caps() argument
1426 u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2]; in cdns_mhdp_link_up()
1442 err = drm_dp_dpcd_read(&mhdp->aux, addr, dpcd, DP_RECEIVER_CAP_SIZE); in cdns_mhdp_link_up()
/linux-6.15/drivers/gpu/drm/bridge/
H A Dtc358767.c351 u8 dpcd[DP_RECEIVER_CAP_SIZE];
836 DP_RECEIVER_CAP_SIZE); in tc_get_display_props()

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