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Searched refs:DPLL (Results 1 – 25 of 27) sorted by relevance

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/linux-6.15/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
37 - reg : offsets for the register set for controlling the DPLL.
43 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
45 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
56 - ti,lock : DPLL locks in programmed rate
57 - ti,min-div : the minimum divisor to start from to round the DPLL
59 - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
61 - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
[all …]
H A Dapll.txt9 a subtype of a DPLL [2], although a simplified one at that.
/linux-6.15/drivers/dpll/
H A DKconfig3 # Generic DPLL drivers configuration
6 config DPLL config
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dmicrochip,sparx5-dpll.yaml7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c1860 intel_de_write(dev_priv, DPLL(dev_priv, pipe), in i9xx_enable_pll()
1865 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i9xx_enable_pll()
1883 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i9xx_enable_pll()
2012 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in _vlv_enable_pll()
2033 intel_de_write(dev_priv, DPLL(dev_priv, pipe), in vlv_enable_pll()
2180 intel_de_write(dev_priv, DPLL(dev_priv, pipe), in chv_enable_pll()
2267 intel_de_write(display, DPLL(display, pipe), val); in vlv_disable_pll()
2268 intel_de_posting_read(display, DPLL(display, pipe)); in vlv_disable_pll()
2286 intel_de_write(display, DPLL(display, pipe), val); in chv_disable_pll()
2287 intel_de_posting_read(display, DPLL(display, pipe)); in chv_disable_pll()
[all …]
H A Dintel_dvo.c462 dpll[pipe] = intel_de_rmw(dev_priv, DPLL(dev_priv, pipe), 0, in intel_dvo_init_dev()
469 intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll[pipe]); in intel_dvo_init_dev()
H A Dintel_dpio_phy.c1173 dpll_reg = DPLL(display, 0); in vlv_wait_port_ready()
1177 dpll_reg = DPLL(display, 0); in vlv_wait_port_ready()
H A Dintel_display_power_well.c1217 u32 val = intel_de_read(display, DPLL(display, pipe)); in vlv_display_power_well_init()
1223 intel_de_write(display, DPLL(display, pipe), val); in vlv_display_power_well_init()
1378 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
H A Dintel_display.c8184 intel_de_write(display, DPLL(display, pipe), in i830_enable_pipe()
8186 intel_de_write(display, DPLL(display, pipe), dpll); in i830_enable_pipe()
8189 intel_de_posting_read(display, DPLL(display, pipe)); in i830_enable_pipe()
8197 intel_de_write(display, DPLL(display, pipe), dpll); in i830_enable_pipe()
8201 intel_de_write(display, DPLL(display, pipe), dpll); in i830_enable_pipe()
8202 intel_de_posting_read(display, DPLL(display, pipe)); in i830_enable_pipe()
8235 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); in i830_disable_pipe()
8236 intel_de_posting_read(display, DPLL(display, pipe)); in i830_disable_pipe()
H A Dintel_pps.c127 pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
H A Dintel_display_power.c1781 u32 status = intel_de_read(display, DPLL(display, PIPE_A)); in chv_phy_control_init()
/linux-6.15/arch/arm64/boot/dts/xilinx/
H A Dxlnx-zynqmp-clk.h15 #define DPLL 3 macro
/linux-6.15/include/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h22 #define DPLL 3 macro
/linux-6.15/arch/arm/mach-omap2/
H A Dsleep24xx.S60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
/linux-6.15/drivers/net/ethernet/mellanox/mlx5/core/
H A DKconfig205 tristate "Mellanox 5th generation network adapters (ConnectX series) DPLL support"
207 select DPLL
209 DPLL support in Mellanox Technologies ConnectX NICs.
/linux-6.15/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi101 /* derived from 600MHz DPLL */
203 /* derived from 600MHz DPLL */
239 /* derived from 600MHz DPLL */
251 /* derived from 600MHz DPLL */
266 /* derived from 600MHz DPLL */
/linux-6.15/Documentation/netlink/specs/
H A Ddpll.yaml5 doc: DPLL subsystem.
465 Get list of DPLL devices (dump) or attributes of a single dpll device
492 doc: Set attributes for a DPLL device
/linux-6.15/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
/linux-6.15/Documentation/driver-api/
H A Ddpll.rst7 DPLL chapter
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
17 DPLL's input and output may be configurable.
160 pick a highest priority valid signal and use it to control the DPLL
/linux-6.15/Documentation/arch/arm/omap/
H A Ddss.rst32 - Use DSI DPLL to create DSS FCK
301 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
/linux-6.15/drivers/ptp/
H A DKconfig220 select DPLL
/linux-6.15/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dreg.h256 #define DPLL 0x034A macro
/linux-6.15/drivers/net/ethernet/intel/
H A DKconfig298 select DPLL
/linux-6.15/arch/arm/boot/dts/rockchip/
H A Drk3036.dtsi238 * Fix the emac parent clock is DPLL instead of APLL.
/linux-6.15/Documentation/networking/device_drivers/hamradio/
H A Dz8530drv.rst308 present at all (BayCom). It feeds back the output of the DPLL

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