Searched refs:DDRPLL (Results 1 – 7 of 7) sorted by relevance
| /linux-6.15/drivers/clk/nuvoton/ |
| H A D | clk-ma35d1-pll.c | 235 case DDRPLL: in ma35d1_clk_pll_recalc_rate()
267 case DDRPLL: in ma35d1_clk_pll_round_rate()
347 if (id == CAPLL || id == DDRPLL) in ma35d1_reg_clk_pll()
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| H A D | clk-ma35d1.c | 504 hws[DDRPLL] = ma35d1_reg_clk_pll(dev, DDRPLL, pllmode[1], "ddrpll", in ma35d1_clocks_probe()
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| /linux-6.15/Documentation/devicetree/bindings/clock/ |
| H A D | nuvoton,ma35d1-clk.yaml | 36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
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| H A D | keystone-pll.txt | 2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
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| /linux-6.15/arch/arm64/boot/dts/nuvoton/ |
| H A D | ma35d1-iot-512m.dts | 42 <&clk DDRPLL>,
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| H A D | ma35d1-som-256m.dts | 42 <&clk DDRPLL>,
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| /linux-6.15/include/dt-bindings/clock/ |
| H A D | nuvoton,ma35d1-clk.h | 21 #define DDRPLL 10 macro
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