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/linux-6.15/Documentation/devicetree/bindings/memory-controllers/
H A Dxlnx,versal-ddrmc-edac.yaml7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
14 The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
24 - description: DDR Memory Controller registers
25 - description: NOC registers corresponding to DDR Memory Controller
H A Dsnps,dw-umctl2-ddrc.yaml14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
19 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
27 description: Synopsys DW uMCTL2 DDR controller v3.80a
29 - description: Synopsys DW uMCTL2 DDR controller
31 - description: Xilinx ZynqMP DDR controller v2.40a
H A Dqca,ath79-ddr-controller.yaml7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
14 flush the FIFO between various devices and the DDR. This is mainly used by
H A Drockchip,rk3399-dmc.yaml20 Node to get DDR loading. Refer to
44 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
131 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
179 frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
226 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
318 Defines the power-down idle disable frequency in Hz. When the DDR
324 Defines the self-refresh idle disable frequency in Hz. When the DDR
331 frequency in Hz. When the DDR frequency is greater than
[all …]
H A Dcalxeda-ddr-ctrlr.yaml7 title: Calxeda DDR memory controller
10 The Calxeda DDR memory controller is initialised and programmed by the
H A Dxlnx,zynq-ddrc-a05.yaml7 title: Zynq A05 DDR Memory Controller
14 The Zynq DDR ECC controller has an optional ECC support in half-bus width
H A Drenesas,dbsc.yaml7 title: Renesas DDR Bus Controllers
15 different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
/linux-6.15/Documentation/devicetree/bindings/mips/brcm/
H A Dsoc.txt45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
95 - reg : the DDR PHY register range and length
104 == DDR memory controller sequencer
106 Control registers for this memory controller's DDR memory sequencer
115 - reg : the DDR sequencer register range and length
136 - reg : the DDR Arbiter register range and length
/linux-6.15/Documentation/admin-guide/perf/
H A Dmeson-ddr-pmu.rst4 Amlogic SoC DDR Bandwidth Performance Monitoring Unit (PMU)
10 to show if the performance bottleneck is on DDR bandwidth.
24 Below are DDR access request event filter keywords:
55 + Show the total DDR bandwidth per seconds:
62 + Show individual DDR bandwidth from CPU and GPU respectively, as well as
H A Dalibaba_pmu.rst9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
43 The DDR Controller (DDRCTL) and DDR PHY combine to create a complete solution
44 for connecting an SoC application bus to DDR memory devices. The DDRCTL
49 the DDR PHY Interface (DFI) to the PHY module, which launches and captures data
H A Dmrvl-odyssey-ddr-pmu.rst2 Marvell Odyssey DDR PMU Performance Monitoring Unit (PMU UNCORE)
8 at the interface between the DDR controller and the PHY, interface between
9 the DDR Controller and the CHI interconnect, or within the DDR Controller.
H A Dimx-ddr.rst2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
69 counting the number of bytes (as opposed to the number of bursts) from DDR
87 PMU in DDR subsystem, only one single port0 exists, so axi_port is reserved
99 monitor data channel from DDR transactions, since data channel is more
/linux-6.15/Documentation/ABI/testing/
H A Dsysfs-driver-bd9571mwv-regulator5 Description: Read/write the current state of DDR Backup Mode, which controls
6 if DDR power rails will be kept powered during system suspend.
10 A. With a momentary power switch (or pulse signal), DDR
26 DDR Backup Mode must be explicitly enabled by the user,
H A Dsysfs-platform-brcmstb-memc7 internal DDR controller clock cycles. Possible values range
15 DDR PHY frequency in Hz.
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dmvebu-core-clock.txt12 4 = dramclk (DDR clock)
18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
H A Dsophgo,sg2042-clkgen.yaml23 - description: DDR PLL 0
24 - description: DDR PLL 1
H A Dsophgo,sg2042-pll.yaml22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
/linux-6.15/Documentation/driver-api/thermal/
H A Dintel_dptf.rst198 DDR (Double Data Rate) and DLVR (Digital Linear Voltage Regulator)
223 management has no other restriction in changing DDR data rates;
225 DDR-RFIM) for Wi-Fi from BIOS.
259 Request the restriction of specific DDR data rate and set this
267 Restricted DDR data rate for RFI protection: Lower Limit
270 Restricted DDR data rate for RFI protection: Upper Limit
273 DDR data rate selection 1st point
276 DDR data rate selection 2nd point
279 DDR data rate selection 3rd point
282 DDR data rate selection 4th point
[all …]
/linux-6.15/drivers/gpio/
H A Dgpio-mb86s7x.c30 #define DDR(x) (0x10 + x / 8 * 4) macro
81 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
83 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
106 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
108 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
/linux-6.15/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
179 Control registers for this memory controller's DDR SHIMPHY.
183 - reg : the DDR SHIMPHY register range
185 == MEMC DDR control
/linux-6.15/drivers/perf/amlogic/
H A DKconfig3 tristate "Amlogic DDR Bandwidth Performance Monitor"
6 Provides support for the DDR performance monitor
/linux-6.15/drivers/mtd/lpddr/
H A DKconfig10 flash chips. Synonymous with Mobile-DDR. It is a new standard for
11 DDR memories, intended for battery-operated systems.
/linux-6.15/arch/arm/mach-omap2/
H A Dsleep24xx.S55 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
75 movs r0, r0 @ see if DDR or SDR
/linux-6.15/Documentation/devicetree/bindings/perf/
H A Damlogic,g12-ddr-pmu.yaml7 title: Amlogic G12 DDR performance monitor
13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
/linux-6.15/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx7ulp-pinctrl.txt4 ports and IOMUXC DDR for DDR interface.

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