Searched refs:DBC (Results 1 – 5 of 5) sorted by relevance
244 (DBC for short) is solely for the use of that workload and is not shared with247 Each DBC is a pair of FIFOs that manage data in and out of the workload. One250 Each DBC contains 4 registers in hardware:265 DBC registers are exposed to the host via the second BAR. Each DBC consumes271 memory must be provided per DBC, which hosts both FIFOs. The request FIFO will411 response FIFO of a DBC. The DMA Bridge hardware has an IRQ storm mitigation452 used by the DBC.490 channel. This notification identifies the workload by it's assigned DBC. A492 DBC/NSPs into a working state.
53 interrupt handlers for every DBC and MHI wake up for every interrupt that54 arrives; however, the DBC threaded irq handlers only are started when work to be57 If the DBC is configured to force MSI interrupts, this can circumvent the124 DMA Bridge, and as such, locks the BO to a specific DBC.166 workload should be allowed to interface with the DBC.
208 if (PSP_FEATURE(psp, DBC) || in psp_init()
453 DBC = 0x38, enumerator
1031 AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER - DBC SUPPORT