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Searched refs:CTS (Results 1 – 25 of 105) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_afmt.c51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument
82 *CTS = cts; in amdgpu_afmt_calc_cts()
85 *N, *CTS, freq); in amdgpu_afmt_calc_cts()
/linux-6.15/arch/arm64/boot/dts/freescale/
H A Dimx8mm-phygate-tauri-l-rs232-rts-cts.dtso6 * Tauri-L RS232 with RTS/CTS hardware flow control:
8 * - UART4_RX becomes CTS
H A Dimx8mm-venice-gw72xx-0x-rs232-rts.dtso5 * GW72xx RS232 with RTS/CTS hardware flow control:
8 * - UART4_RX becomes CTS
H A Dimx8mm-venice-gw73xx-0x-rs232-rts.dtso5 * GW73xx RS232 with RTS/CTS hardware flow control:
8 * - UART4_RX becomes CTS
H A Dimx8mp-dhcom-drc02.dts184 * DHCOM UART1 RTS/CTS pins. Therefore this UART have to use DHCOM GPIOs
185 * for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS.
197 * controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property
H A Dimx8mq-hummingboard-pulse.dts166 * reconfigured to enable RTS/CTS on UART3
209 * Header. To use RTS/CTS on UART3 comment them out
/linux-6.15/Documentation/ABI/testing/
H A Dsysfs-class-led-trigger-tty28 CTS = Clear To Send
31 If set to 0 (default), the LED will not evaluate CTS.
32 If set to 1, the LED will evaluate CTS.
/linux-6.15/drivers/crypto/intel/keembay/
H A DKconfig31 bool "Support for Intel Keem Bay OCS AES/SM4 CTS HW acceleration"
35 AES/SM4 CBC with CTS mode hardware acceleration for use with
40 Intel does not recommend use of CTS mode with AES/SM4.
/linux-6.15/arch/arm/boot/dts/st/
H A Dstm32mp153c-lxa-fairytux2-gen1.dts94 * On Gen 1 FairyTux 2 only RTS can be used and not CTS as well,
95 * Because pins PD11 (CTS) and PI11 (USER_BTN1) share the same
H A Dste-dbx5x0-pinctrl.dtsi17 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
28 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
75 pins = "GPIO6_AF6"; /* CTS */
86 pins = "GPIO6_AF6"; /* CTS */
H A Dstm32mp157a-iot-box.dts57 /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */
/linux-6.15/Documentation/devicetree/bindings/serial/
H A Dserial.yaml32 the UART's CTS line.
68 for RTS/CTS hardware flow control, and that they are available for use
78 description: CTS and RTS pins are swapped.
H A Dmicrochip,pic32-uart.txt14 - cts-gpios: CTS pin for UART
H A Dcirrus,clps711x-uart.txt11 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
/linux-6.15/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-dhcom-drc02.dts23 * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
24 * Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1
H A Dimx6ul-ccimx6ulsbcpro.dts62 /* CAN2 is multiplexed with UART2 RTS/CTS */
200 /* UART2 RTS/CTS muxed with CAN2 */
208 /* UART3 RTS/CTS muxed with CAN 1 */
/linux-6.15/arch/riscv/crypto/
H A DKconfig6 tristate "Ciphers: AES, modes: ECB, CBC, CTS, CTR, XTS"
13 Length-preserving ciphers: AES with ECB, CBC, CTS, CTR, XTS
/linux-6.15/arch/arm/boot/dts/ti/omap/
H A Dam335x-netcom-plus-2xx.dts25 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */
38 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */
/linux-6.15/Documentation/usb/
H A Diuu_phoenix.rst44 0=none, 1=CD, 2=!CD, 3=DSR, 4=!DSR, 5=CTS, 6=!CTS, 7=RING, 8=!RING (int)
/linux-6.15/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-orangepi-win.dts382 /* On Pi-2 connector, RTS/CTS optional */
389 /* On Pi-2 connector, RTS/CTS optional */
396 /* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */
H A Dsun50i-a64-pine64.dts285 /* On Wifi/BT connector, with RTS/CTS */
306 /* On Euler connector, RTS/CTS optional */
/linux-6.15/Documentation/devicetree/bindings/crypto/
H A Dsamsung-slimsss.yaml15 -- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS
/linux-6.15/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dserial.txt14 CTS, RTS, DCD, DSR, DTR, and RI.
/linux-6.15/drivers/tty/
H A Dnozomi.c222 unsigned int CTS:1; member
283 unsigned int CTS:1; member
902 if (old_ctrl.CTS == 1 && ctrl_dl.CTS == 0) { in receive_flow_control()
907 } else if (old_ctrl.CTS == 0 && ctrl_dl.CTS == 1) { in receive_flow_control()
925 if (old_ctrl.CTS != ctrl_dl.CTS) in receive_flow_control()
1599 if (port->ctrl_dl.CTS) { in ntty_write()
1649 | (ctrl_dl->CTS ? TIOCM_CTS : 0); in ntty_tiocmget()
/linux-6.15/arch/arm64/boot/dts/renesas/
H A Dr9a08g045s33-smarc-pmod1-type-3a.dtso36 <RZG2L_PORT_PINMUX(16, 0, 1)>, /* CTS# */

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