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Searched refs:CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2869 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x00000010 macro
H A Dgfx_7_2_sh_mask.h3130 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 macro
H A Dgfx_8_0_sh_mask.h3744 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 macro
H A Dgfx_8_1_sh_mask.h4266 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1224 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT … macro
H A Dgc_9_1_sh_mask.h1123 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h1090 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h1140 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h1723 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h3728 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h6575 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h7016 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h6711 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h7350 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h6977 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT … macro