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Searched refs:CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h1830 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 macro
H A Dgfx_8_1_sh_mask.h2354 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11964 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT … macro
H A Dgc_9_1_sh_mask.h13390 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h13164 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h15177 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h3368 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h13087 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h16393 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h18933 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h18636 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h17278 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT … macro