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Searched refs:CP_INT_STATUS__PRIV_REG_INT_STAT_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2478 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L macro
H A Dgfx_7_2_sh_mask.h1253 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000 macro
H A Dgfx_8_0_sh_mask.h1599 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000 macro
H A Dgfx_8_1_sh_mask.h2123 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h10812 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK … macro
H A Dgc_9_1_sh_mask.h12289 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK … macro
H A Dgc_9_2_1_sh_mask.h12093 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK … macro
H A Dgc_9_4_3_sh_mask.h13820 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK … macro
H A Dgc_9_4_2_sh_mask.h2109 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK … macro
H A Dgc_11_5_0_sh_mask.h12056 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK … macro
H A Dgc_11_0_0_sh_mask.h15240 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK … macro
H A Dgc_12_0_0_sh_mask.h11724 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK … macro
H A Dgc_10_1_0_sh_mask.h17734 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK … macro
H A Dgc_11_0_3_sh_mask.h17395 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK … macro
H A Dgc_10_3_0_sh_mask.h15994 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK … macro