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Searched refs:CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h1595 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000 macro
H A Dgfx_8_1_sh_mask.h2119 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h10810 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK … macro
H A Dgc_9_1_sh_mask.h12287 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK … macro
H A Dgc_9_2_1_sh_mask.h12091 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK … macro
H A Dgc_9_4_3_sh_mask.h13818 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK … macro
H A Dgc_9_4_2_sh_mask.h2107 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK … macro
H A Dgc_11_5_0_sh_mask.h12054 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK … macro
H A Dgc_11_0_0_sh_mask.h15238 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK … macro
H A Dgc_12_0_0_sh_mask.h11722 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK … macro
H A Dgc_10_1_0_sh_mask.h17732 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK … macro
H A Dgc_11_0_3_sh_mask.h17393 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK … macro
H A Dgc_10_3_0_sh_mask.h15992 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK … macro