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Searched refs:CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2398 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L macro
H A Dgfx_7_2_sh_mask.h1207 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 macro
H A Dgfx_8_0_sh_mask.h1541 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 macro
H A Dgfx_8_1_sh_mask.h2065 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11044 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12521 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12325 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h14052 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2341 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12260 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15444 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17987 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17599 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h16251 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK … macro