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Searched refs:CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK (Results 1 – 25 of 25) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v12.c68 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in init_interrupts_v12()
H A Damdgpu_amdkfd_gfx_v7.c128 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
H A Damdgpu_amdkfd_gfx_v8.c123 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
H A Damdgpu_amdkfd_gfx_v10_3.c121 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in init_interrupts_v10_3()
H A Damdgpu_amdkfd_gfx_v11.c117 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in init_interrupts_v11()
H A Damdgpu_amdkfd_gfx_v10.c152 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
H A Dgfx_v7_0.c4632 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
4637 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
4683 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_compute_eop_interrupt_state()
4688 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_compute_eop_interrupt_state()
H A Damdgpu_amdkfd_gfx_v9.c172 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_gfx_v9_init_interrupts()
H A Dgfx_v6_0.c3212 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state()
3217 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state()
H A Dgfx_v8_0.c6453 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v8_0_set_compute_eop_interrupt_state()
6458 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v8_0_set_compute_eop_interrupt_state()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2382 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L macro
H A Dgfx_7_2_sh_mask.h1185 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 macro
H A Dgfx_8_0_sh_mask.h1513 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 macro
H A Dgfx_8_1_sh_mask.h2037 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11012 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12489 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12293 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h14020 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2309 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12238 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15422 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h11858 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17953 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17577 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h16217 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK … macro