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Searched refs:CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK (Results 1 – 19 of 19) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v12.c125 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in init_mqd()
H A Dkfd_mqd_manager_v10.c111 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in init_mqd()
H A Dkfd_mqd_manager_v11.c158 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in init_mqd()
H A Dkfd_mqd_manager_v9.c187 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in init_mqd()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2873 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | in gfx_v7_0_mqd_init()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h3355 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 macro
H A Dgfx_8_0_sh_mask.h3971 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 macro
H A Dgfx_8_1_sh_mask.h4493 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12920 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
H A Dgc_9_1_sh_mask.h14220 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
H A Dgc_9_2_1_sh_mask.h14085 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
H A Dgc_9_4_3_sh_mask.h16452 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
H A Dgc_9_4_2_sh_mask.h4018 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
H A Dgc_11_5_0_sh_mask.h14091 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
H A Dgc_11_0_0_sh_mask.h17397 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
H A Dgc_12_0_0_sh_mask.h13295 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
H A Dgc_10_1_0_sh_mask.h20331 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
H A Dgc_11_0_3_sh_mask.h19636 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro
H A Dgc_10_3_0_sh_mask.h18484 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK … macro