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Searched refs:CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h3397 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000 macro
H A Dgfx_8_0_sh_mask.h4019 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000 macro
H A Dgfx_8_1_sh_mask.h4541 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12971 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK … macro
H A Dgc_9_1_sh_mask.h14271 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK … macro
H A Dgc_9_2_1_sh_mask.h14136 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK … macro
H A Dgc_9_4_3_sh_mask.h16505 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK … macro
H A Dgc_9_4_2_sh_mask.h4069 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK … macro
H A Dgc_11_5_0_sh_mask.h14146 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK … macro
H A Dgc_11_0_0_sh_mask.h17452 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK … macro
H A Dgc_12_0_0_sh_mask.h13348 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK … macro
H A Dgc_10_1_0_sh_mask.h20386 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK … macro
H A Dgc_11_0_3_sh_mask.h19693 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK … macro
H A Dgc_10_3_0_sh_mask.h18539 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK … macro