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Searched refs:CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h2690 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 macro
H A Dgfx_8_0_sh_mask.h3262 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 macro
H A Dgfx_8_1_sh_mask.h3784 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h19430 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT … macro
H A Dgc_9_1_sh_mask.h20737 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h20664 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h22794 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h12891 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h22837 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h26825 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h14654 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h27344 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h29325 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h25605 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT … macro