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Searched refs:CDCLK_FREQ_SEL_MASK (Results 1 – 2 of 2) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c987 switch (cdctl & CDCLK_FREQ_SEL_MASK) { in skl_get_cdclk()
1001 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); in skl_get_cdclk()
1005 switch (cdctl & CDCLK_FREQ_SEL_MASK) { in skl_get_cdclk()
1019 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); in skl_get_cdclk()
1165 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); in skl_set_cdclk()
1179 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); in skl_set_cdclk()
1224 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | in skl_sanitize_cdclk()
/linux-6.15/drivers/gpu/drm/i915/
H A Di915_reg.h3800 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) macro
3801 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
3802 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
3803 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
3804 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)