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Searched refs:APLL (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/Documentation/devicetree/bindings/clock/ti/
H A Dapll.txt1 Binding for Texas Instruments APLL clock.
4 register-mapped APLL with usually two selectable input clocks
8 modes (locked, low power stop etc.) APLL mostly behaves like
18 - reg : address and length of the register set for controlling the APLL.
/linux-6.15/arch/arm64/boot/dts/xilinx/
H A Dxlnx-zynqmp-clk.h14 #define APLL 2 macro
/linux-6.15/include/dt-bindings/clock/
H A Dxlnx-versal-clk.h27 #define APLL 18 macro
H A Dxlnx-zynqmp-clk.h21 #define APLL 2 macro
H A Dnuvoton,ma35d1-clk.h22 #define APLL 11 macro
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dnuvoton,ma35d1-clk.yaml36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
/linux-6.15/arch/arm64/boot/dts/nuvoton/
H A Dma35d1-iot-512m.dts43 <&clk APLL>,
H A Dma35d1-som-256m.dts43 <&clk APLL>,
/linux-6.15/drivers/clk/nuvoton/
H A Dclk-ma35d1-pll.c236 case APLL: in ma35d1_clk_pll_recalc_rate()
268 case APLL: in ma35d1_clk_pll_round_rate()
H A Dclk-ma35d1.c506 hws[APLL] = ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", in ma35d1_clocks_probe()
/linux-6.15/drivers/clk/ingenic/
H A Djz4780-cgu.c295 .pll = DEF_PLL(APLL),
/linux-6.15/Documentation/devicetree/bindings/arm/marvell/
H A Dcp110-system-controller.txt35 - 0 0 APLL
/linux-6.15/arch/arm/boot/dts/rockchip/
H A Drk3036.dtsi238 * Fix the emac parent clock is DPLL instead of APLL.