Searched refs:AMDGPU_MAX_MES_PIPES (Results 1 – 4 of 4) sorted by relevance
62 AMDGPU_MAX_MES_PIPES = 2, enumerator79 uint32_t fw_version[AMDGPU_MAX_MES_PIPES];94 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];95 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];96 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];100 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES];101 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];102 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES];106 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES];119 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES];[all …]
990 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v12_0_enable()1060 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v12_0_set_ucode_start_addr()1510 (AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) : in mes_v12_0_sw_init()1516 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v12_0_sw_init()1552 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v12_0_sw_fini()1805 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v12_0_early_init()
904 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v11_0_get_fw_version()942 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v11_0_enable()1403 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v11_0_sw_init()1454 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v11_0_sw_fini()1693 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { in mes_v11_0_early_init()
140 for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) in amdgpu_mes_init()162 for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { in amdgpu_mes_init()202 for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { in amdgpu_mes_init()226 for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { in amdgpu_mes_fini()