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Searched refs:n_width (Results 1 – 2 of 2) sorted by relevance

/freebsd-14.2/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c98 uint32_t n_width; member
498 *n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in get_divisors()
510 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in set_divisors()
712 if (n >= (1 << mnp_bits->n_width)) in pll_set_std()
735 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pll_set_std()
834 if (n >= (1 << mnp_bits->n_width)) in plld2_set_freq()
901 if (n >= (1 << mnp_bits->n_width)) in pllx_set_freq()
922 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pllx_set_freq()
/freebsd-14.2/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c123 uint32_t n_width; member
691 *n = get_masked(val, mnp_bits->n_shift, mnp_bits->n_width); in get_divisors()
703 val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width); in set_divisors()
910 if (n >= (1 << mnp_bits->n_width)) in pll_set_std()
933 reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width); in pll_set_std()
1057 if (n >= (1 << mnp_bits->n_width)) in plld2_set_freq()
1139 if (n >= (1 << mnp_bits->n_width)) in pllx_set_freq()
1193 mnp_bits->n_width); in pllx_set_freq()