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Searched refs:input_reg (Results 1 – 17 of 17) sorted by relevance

/freebsd-14.2/sys/arm/freescale/imx/
H A Dimx_iomux.c94 uint32_t input_reg; member
164 iomux_configure_input(sc, cfg->input_reg, cfg->input_val); in iomux_configure_pins()
174 cfg->input_reg, cfg->input_val, in iomux_configure_pins()
/freebsd-14.2/sys/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imx8ulp-pinctrl.yaml35 setting for one pin. The first 4 integers <mux_config_reg input_reg
46 "input_reg" indicates the offset of select input register.
H A Dfsl,imx8mm-pinctrl.yaml35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
H A Dfsl,imx8mq-pinctrl.yaml35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
H A Dfsl,imx93-pinctrl.yaml38 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
51 "input_reg" indicates the offset of select input register.
H A Dfsl,imx8mp-pinctrl.yaml35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
H A Dfsl,imxrt1170.yaml36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "input_reg" indicates the offset of select input register.
H A Dfsl,imxrt1050.yaml36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "input_reg" indicates the offset of select input register.
H A Dfsl,imx8mn-pinctrl.yaml35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
H A Dfsl,imx8m-pinctrl.yaml39 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
53 "input_reg" indicates the offset of select input register.
H A Dfsl,imx7d-pinctrl.yaml44 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
57 "input_reg" indicates the offset of select input register.
H A Dfsl,imx6sx-pinctrl.txt9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
H A Dfsl,imx6ul-pinctrl.txt10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
H A Dfsl,imx6sll-pinctrl.txt9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
H A Dfsl,imx7ulp-pinctrl.txt17 <mux_conf_reg input_reg mux_mode input_val> are specified
H A Dfsl,imx7d-pinctrl.txt32 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
H A Dfsl,imx-pinctrl.txt26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val