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Searched refs:getOpcodeDef (Results 1 – 11 of 11) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp79 auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI); in matchExtractVecEltPairwiseAdd()
91 getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op2, MRI); in matchExtractVecEltPairwiseAdd()
94 Shuffle = getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op1, MRI); in matchExtractVecEltPairwiseAdd()
355 auto *BV1 = getOpcodeDef<GBuildVector>(BVO1, MRI); in matchOrToBSP()
356 auto *BV2 = getOpcodeDef<GBuildVector>(BVO2, MRI); in matchOrToBSP()
H A DAArch64PostLegalizerLowering.cpp334 auto *InsMI = getOpcodeDef(TargetOpcode::G_INSERT_VECTOR_ELT, in matchDupFromInsertVectorElt()
339 if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(), in matchDupFromInsertVectorElt()
359 auto *BuildVecMI = getOpcodeDef(TargetOpcode::G_BUILD_VECTOR, in matchDupFromBuildVector()
428 if (!getOpcodeDef<GImplicitDef>(V2, MRI) || in matchEXT()
1104 MachineInstr *Ext = getOpcodeDef(AArch64::G_EXT, Unmerge.getSourceReg(), MRI); in matchUnmergeExtToUnmerge()
1115 if (!getOpcodeDef<GImplicitDef>(ExtSrc2, MRI)) in matchUnmergeExtToUnmerge()
H A DAArch64InstructionSelector.cpp1706 MachineInstr *AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); in tryOptCompareBranchFedByICmp()
1750 AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); in tryOptCompareBranchFedByICmp()
2340 return getOpcodeDef(TargetOpcode::G_ICMP, Reg, MRI); in earlySelect()
2347 auto *Cmp = getOpcodeDef(TargetOpcode::G_ICMP, ZExt, MRI); in earlySelect()
3330 auto *LoadMI = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI); in select()
5332 MachineInstr *Extract = getOpcodeDef(TargetOpcode::G_EXTRACT_VECTOR_ELT, in selectUSMovFromExtend()
5871 else if ((OpMI = getOpcodeDef(TargetOpcode::G_FCONSTANT, in tryOptConstantBuildVec()
5901 return !getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Op.getReg(), MRI); in tryOptBuildVecToSubregToReg()
7072 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeShiftedExtendXReg()
7133 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeXRO()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h219 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
274 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { in getOpcodeDef() function
H A DLegalizationArtifactCombiner.h370 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, in tryFoldImplicitDef()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp854 if (auto *LoadMI = getOpcodeDef<GSExtLoad>(LoadUser, MRI)) { in matchSextTruncSextLoad()
884 auto *LoadDef = getOpcodeDef<GLoad>(SrcReg, MRI); in matchSextInRegOfLoad()
961 auto *Addr = getOpcodeDef<GPtrAdd>(MI->getPointerReg(), MRI); in canFoldInAddressingMode()
1034 if (getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Ptr, MRI)) in findPostIndexCandidate()
1173 auto *LoadMI = getOpcodeDef<GLoad>(MI.getOperand(1).getReg(), MRI); in matchCombineExtractedVectorLoad()
1941 auto *Unmerge = getOpcodeDef<GUnmerge>(MergedValues[0], MRI); in matchCombineMergeUnmerge()
1968 auto *SrcInstr = getOpcodeDef<GMergeLikeInstr>(SrcReg, MRI); in matchCombineUnmergeMergeToPlainValues()
3624 auto *Load = getOpcodeDef<GZExtLoad>(MaybeLoad, MRI); in matchLoadAndBytePosition()
4513 auto *Src1Def = getOpcodeDef<GPtrAdd>(Src1Reg, MRI); in reassociationCanBreakAddressingModePattern()
5090 auto *RHSDef = getOpcodeDef<GBuildVector>(RHS, MRI); in buildUDivUsingMul()
[all …]
H A DUtils.cpp626 MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg, in getOpcodeDef() function in llvm
768 auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2, MRI); in ConstantFoldVectorBinop()
772 auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1, MRI); in ConstantFoldVectorBinop()
978 auto *BV = getOpcodeDef<GBuildVector>(Src, MRI); in ConstantFoldCTLZ()
1359 getOpcodeDef<GImplicitDef>(BV->getSourceReg(SrcIdx), MRI)) in isConstantOrConstantVector()
H A DLegalizerHelper.cpp8254 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI); in lowerMemset()
8407 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI); in lowerMemcpy()
8515 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI); in lowerMemmove()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp3671 if (MachineInstr *SrcFNeg = getOpcodeDef(AMDGPU::G_FNEG, ModSrc, MRI)) { in stripAnySourceMods()
3673 if (MachineInstr *SrcFAbs = getOpcodeDef(AMDGPU::G_FABS, ModSrc, MRI)) in stripAnySourceMods()
3675 } else if (MachineInstr *SrcFAbs = getOpcodeDef(AMDGPU::G_FABS, ModSrc, MRI)) in stripAnySourceMods()
H A DAMDGPUInstructionSelector.cpp2681 MachineInstr *Fabs = getOpcodeDef(TargetOpcode::G_FABS, Src, *MRI); in selectG_FNEG()
5120 = getOpcodeDef(TargetOpcode::G_PTR_ADD, Data.N0, *MRI)) { in parseMUBUFAddress()
H A DAMDGPURegisterBankInfo.cpp1295 MachineInstr *Add = getOpcodeDef(AMDGPU::G_ADD, CombinedOffset, *MRI); in setBufferOffsets()