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Searched refs:WriteRes (Results 1 – 25 of 64) sorted by relevance

123

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFiveP400.td58 def : WriteRes<WriteJmp, [SiFiveP400Branch]>;
59 def : WriteRes<WriteJal, [SiFiveP400Branch]>;
116 def : WriteRes<WriteSTB, [SiFiveP400Store]>;
117 def : WriteRes<WriteSTH, [SiFiveP400Store]>;
118 def : WriteRes<WriteSTW, [SiFiveP400Store]>;
125 def : WriteRes<WriteLDB, [SiFiveP400Load]>;
126 def : WriteRes<WriteLDH, [SiFiveP400Load]>;
129 def : WriteRes<WriteLDW, [SiFiveP400Load]>;
130 def : WriteRes<WriteLDD, [SiFiveP400Load]>;
240 def : WriteRes<WriteCSR, [SiFiveP400SYS]>;
[all …]
H A DRISCVSchedSyntacoreSCR1.td93 def : WriteRes<WriteFAdd32, []>;
96 def : WriteRes<WriteFAdd64, []>;
111 def : WriteRes<WriteFCmp32, []>;
112 def : WriteRes<WriteFCmp64, []>;
117 def : WriteRes<WriteFMul32, []>;
118 def : WriteRes<WriteFMA32, []>;
119 def : WriteRes<WriteFMul64, []>;
120 def : WriteRes<WriteFMA64, []>;
126 def : WriteRes<WriteSFB, []>;
130 def : WriteRes<WriteCSR, []>;
[all …]
H A DRISCVSchedRocket.td51 def : WriteRes<WriteJmp, [RocketUnitB]>;
52 def : WriteRes<WriteJal, [RocketUnitB]>;
53 def : WriteRes<WriteJalr, [RocketUnitB]>;
81 def : WriteRes<WriteSTB, [RocketUnitMem]>;
82 def : WriteRes<WriteSTH, [RocketUnitMem]>;
83 def : WriteRes<WriteSTW, [RocketUnitMem]>;
84 def : WriteRes<WriteSTD, [RocketUnitMem]>;
89 def : WriteRes<WriteLDB, [RocketUnitMem]>;
90 def : WriteRes<WriteLDH, [RocketUnitMem]>;
172 def : WriteRes<WriteCSR, []>;
[all …]
H A DRISCVScheduleZb.td101 def : WriteRes<WriteCLZ, []>;
102 def : WriteRes<WriteCLZ32, []>;
103 def : WriteRes<WriteCTZ, []>;
104 def : WriteRes<WriteCTZ32, []>;
105 def : WriteRes<WriteCPOP, []>;
107 def : WriteRes<WriteREV8, []>;
108 def : WriteRes<WriteORCB, []>;
127 def : WriteRes<WriteCLMUL, []>;
137 def : WriteRes<WriteBEXT, []>;
148 def : WriteRes<WritePACK, []>;
[all …]
H A DRISCVSchedSiFive7.td238 def : WriteRes<WriteJmp, [SiFive7PipeB]>;
239 def : WriteRes<WriteJal, [SiFive7PipeB]>;
284 def : WriteRes<WriteCLZ, [SiFive7PipeB]>;
286 def : WriteRes<WriteCTZ, [SiFive7PipeB]>;
315 def : WriteRes<WriteSTB, [SiFive7PipeA]>;
316 def : WriteRes<WriteSTH, [SiFive7PipeA]>;
317 def : WriteRes<WriteSTW, [SiFive7PipeA]>;
318 def : WriteRes<WriteSTD, [SiFive7PipeA]>;
324 def : WriteRes<WriteLDB, [SiFive7PipeA]>;
325 def : WriteRes<WriteLDH, [SiFive7PipeA]>;
[all …]
H A DRISCVSchedule.td206 def : WriteRes<WriteFAdd16, []>;
216 def : WriteRes<WriteFDiv16, []>;
217 def : WriteRes<WriteFCmp16, []>;
218 def : WriteRes<WriteFLD16, []>;
219 def : WriteRes<WriteFMA16, []>;
221 def : WriteRes<WriteFMul16, []>;
225 def : WriteRes<WriteFST16, []>;
252 def : WriteRes<WriteSFB, []>;
264 def : WriteRes<WriteFLI16, []>;
265 def : WriteRes<WriteFLI32, []>;
[all …]
H A DRISCVScheduleV.td755 def : WriteRes<WriteVSETVL, []>;
788 def : WriteRes<WriteVLD1R, []>;
789 def : WriteRes<WriteVLD2R, []>;
790 def : WriteRes<WriteVLD4R, []>;
791 def : WriteRes<WriteVLD8R, []>;
792 def : WriteRes<WriteVST1R, []>;
793 def : WriteRes<WriteVST2R, []>;
794 def : WriteRes<WriteVST4R, []>;
795 def : WriteRes<WriteVST8R, []>;
932 def : WriteRes<WriteVMov1V, []>;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td71 def : WriteRes<WriteImm, []> { let Unsupported = 1; }
72 def : WriteRes<WriteI, []> { let Unsupported = 1; }
73 def : WriteRes<WriteISReg, []> { let Unsupported = 1; }
74 def : WriteRes<WriteIEReg, []> { let Unsupported = 1; }
75 def : WriteRes<WriteExtr, []> { let Unsupported = 1; }
76 def : WriteRes<WriteIS, []> { let Unsupported = 1; }
77 def : WriteRes<WriteID32, []> { let Unsupported = 1; }
78 def : WriteRes<WriteID64, []> { let Unsupported = 1; }
79 def : WriteRes<WriteIM32, []> { let Unsupported = 1; }
80 def : WriteRes<WriteIM64, []> { let Unsupported = 1; }
[all …]
H A DAArch64SchedKryo.td68 def : WriteRes<WriteISReg, [KryoUnitXY, KryoUnitXY]>
70 def : WriteRes<WriteIEReg, [KryoUnitXY, KryoUnitXY]>
72 def : WriteRes<WriteExtr, [KryoUnitXY, KryoUnitX]>
75 def : WriteRes<WriteID32, [KryoUnitXA, KryoUnitY]>
77 def : WriteRes<WriteID64, [KryoUnitXA, KryoUnitY]>
89 def : WriteRes<WriteF, [KryoUnitXY, KryoUnitXY]>
95 def : WriteRes<WriteFMul, [KryoUnitX, KryoUnitX]>
97 def : WriteRes<WriteFDiv, [KryoUnitXA, KryoUnitY]>
104 def : WriteRes<WriteSys, []> { let Latency = 1; }
105 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
[all …]
H A DAArch64SchedThunderX.td60 def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
65 def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
71 def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
76 def : WriteRes<WriteID64, [THXT8XUnitDiv]> {
87 def : WriteRes<WriteVLD, [THXT8XUnitLdSt]> {
127 def : WriteRes<WriteVST, [THXT8XUnitLdSt]>;
143 def : WriteRes<WriteBr, [THXT8XUnitBr]>;
145 def : WriteRes<WriteBrReg, [THXT8XUnitBr]>;
148 def : WriteRes<WriteSys, [THXT8XUnitBr]>;
149 def : WriteRes<WriteBarrier, [THXT8XUnitBr]>;
[all …]
H A DAArch64SchedA53.td61 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
62 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
65 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
85 def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
99 def : WriteRes<WriteAdr, []> { let Latency = 0; }
116 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
119 def : WriteRes<WriteBr, [A53UnitB]>;
120 def : WriteRes<WriteBrReg, [A53UnitB]>;
121 def : WriteRes<WriteSys, [A53UnitB]>;
122 def : WriteRes<WriteBarrier, [A53UnitB]>;
[all …]
H A DAArch64SchedA55.td78 def : WriteRes<WriteID32, [CortexA55UnitDiv]> {
81 def : WriteRes<WriteID64, [CortexA55UnitDiv]> {
86 def : WriteRes<WriteLD, [CortexA55UnitLd]> { let Latency = 3; }
93 def : WriteRes<WriteVLD, [CortexA55UnitLd]> { let Latency = 6;
117 def : WriteRes<WriteAdr, []> { let Latency = 0; }
138 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
141 def : WriteRes<WriteBr, [CortexA55UnitB]>;
142 def : WriteRes<WriteBrReg, [CortexA55UnitB]>;
143 def : WriteRes<WriteSys, [CortexA55UnitB]>;
144 def : WriteRes<WriteBarrier, [CortexA55UnitB]>;
[all …]
H A DAArch64SchedCyclone.td134 def : WriteRes<WriteImm, [CyUnitI]>;
153 def : WriteRes<WriteI, [CyUnitI]>;
159 def : WriteRes<WriteISReg, [CyUnitIS]> {
167 def : WriteRes<WriteIEReg, [CyUnitIS]> {
174 def : WriteRes<WriteIS, [CyUnitIS]>;
195 def : WriteRes<WriteIM32, [CyUnitIM]> {
199 def : WriteRes<WriteIM64, [CyUnitIM]> {
227 def : WriteRes<WriteLD, [CyUnitLS]> {
237 def : WriteRes<WriteST, [CyUnitLS]> {
269 def : WriteRes<WriteAdr, [CyUnitI]>;
[all …]
H A DAArch64SchedTSV110.td68 def : WriteRes<WriteID32, [TSV110UnitMDU]> { let Latency = 12;
70 def : WriteRes<WriteID64, [TSV110UnitMDU]> { let Latency = 20;
78 def : WriteRes<WriteLDHi, []> { let Latency = 4; }
89 def : WriteRes<WriteF, [TSV110UnitF]> { let Latency = 2; }
90 def : WriteRes<WriteFCmp, [TSV110UnitF]> { let Latency = 3; }
92 def : WriteRes<WriteFCopy, [TSV110UnitF]> { let Latency = 2; }
94 def : WriteRes<WriteFMul, [TSV110UnitF]> { let Latency = 5; }
106 def : WriteRes<WriteSys, []> { let Latency = 1; }
107 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
108 def : WriteRes<WriteHint, []> { let Latency = 1; }
[all …]
H A DAArch64SchedAmpere1.td598 def : WriteRes<WriteID32, [Ampere1UnitBS]> {
601 def : WriteRes<WriteID64, [Ampere1UnitBS]> {
604 def : WriteRes<WriteIM32, [Ampere1UnitBS]> {
607 def : WriteRes<WriteIM64, [Ampere1UnitBS]> {
610 def : WriteRes<WriteBr, [Ampere1UnitA]>;
612 def : WriteRes<WriteLD, [Ampere1UnitL]> {
615 def : WriteRes<WriteST, [Ampere1UnitS]> {
622 def : WriteRes<WriteAdr, [Ampere1UnitAB]>;
631 def : WriteRes<WriteF, [Ampere1UnitXY]> {
634 def : WriteRes<WriteFCmp, [Ampere1UnitX]> {
[all …]
H A DAArch64SchedAmpere1B.td560 def : WriteRes<WriteIM32, [Ampere1BUnitBS]> {
566 def : WriteRes<WriteBr, [Ampere1BUnitA]>;
568 def : WriteRes<WriteLD, [Ampere1BUnitL]> {
571 def : WriteRes<WriteST, [Ampere1BUnitS]> {
578 def : WriteRes<WriteAdr, [Ampere1BUnitAB]>;
587 def : WriteRes<WriteF, [Ampere1BUnitXY]> {
590 def : WriteRes<WriteFCmp, [Ampere1BUnitX]> {
593 def : WriteRes<WriteFCvt, [Ampere1BUnitXY]> {
596 def : WriteRes<WriteFCopy, [Ampere1BUnitXY]> {
598 def : WriteRes<WriteFImm, [Ampere1BUnitXY]> {
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleSLM.td67 def : WriteRes<SchedRW, ExePorts> {
89 def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;
90 def : WriteRes<WriteZero, []>;
139 def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
155 def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
187 def : WriteRes<WriteFStore, [SLM_MEC_RSV]>;
188 def : WriteRes<WriteFStoreX, [SLM_MEC_RSV]>;
190 def : WriteRes<WriteFStoreNT, [SLM_MEC_RSV]>;
191 def : WriteRes<WriteFStoreNTX, [SLM_MEC_RSV]>;
460 def : WriteRes<WriteFence, [SLM_MEC_RSV]>;
[all …]
H A DX86ScheduleAtom.td63 def : WriteRes<SchedRW, RRPorts> {
70 def : WriteRes<SchedRW.Folded, RMPorts> {
78 def : WriteRes<WriteRMW, [AtomPort0]>;
122 def : WriteRes<WriteSETCC, [AtomPort01]>;
139 def : WriteRes<WriteLEA, [AtomPort1]>;
171 def : WriteRes<WriteLoad, [AtomPort0]>;
172 def : WriteRes<WriteStore, [AtomPort0]>;
173 def : WriteRes<WriteStoreNT, [AtomPort0]>;
174 def : WriteRes<WriteMove, [AtomPort01]>;
185 def : WriteRes<WriteZero, []>;
[all …]
H A DX86SchedSandyBridge.td91 def : WriteRes<SchedRW, ExePorts> {
108 def : WriteRes<WriteRMW, [SBPort23,SBPort4]>;
113 def : WriteRes<WriteMove, [SBPort015]>;
120 def : WriteRes<WriteZero, []>;
144 def : WriteRes<WriteIMulHLd, []> {
196 def : WriteRes<WriteLEA, [SBPort01]>;
488 def : WriteRes<WritePCmpIStrM, [SBPort0]> {
510 def : WriteRes<WritePCmpIStrI, [SBPort0]> {
549 def : WriteRes<WriteAESIMC, [SBPort5]> {
570 def : WriteRes<WriteCLMul, [SBPort015]> {
[all …]
H A DX86SchedSkylakeClient.td95 def : WriteRes<SchedRW, ExePorts> {
112 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
133 def : WriteRes<WriteIMulHLd, []> {
167 def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
217 def : WriteRes<WriteZero, []>;
424 def : WriteRes<WriteVecInsert, [SKLPort5]> {
494 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
518 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
582 def : WriteRes<WriteCLMul, [SKLPort5]> {
607 def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM7.td72 def : WriteRes<WriteMUL16, [M7UnitMAC]>;
73 def : WriteRes<WriteMUL32, [M7UnitMAC]>;
88 def : WriteRes<WriteDIV, [M7UnitALU]> {
155 def : WriteRes<WriteVLD1, []>;
156 def : WriteRes<WriteVLD2, []>;
157 def : WriteRes<WriteVLD3, []>;
158 def : WriteRes<WriteVLD4, []>;
159 def : WriteRes<WriteVST1, []>;
160 def : WriteRes<WriteVST2, []>;
161 def : WriteRes<WriteVST3, []>;
[all …]
H A DARMScheduleM85.td96 def : WriteRes<WriteMAC16, [M85UnitMAC]>;
97 def : WriteRes<WriteMAC32, [M85UnitMAC]>;
103 def : WriteRes<WriteDIV, [M85UnitDiv]> {
972 def : WriteRes<WriteVLD1, []>;
973 def : WriteRes<WriteVLD2, []>;
974 def : WriteRes<WriteVLD3, []>;
975 def : WriteRes<WriteVLD4, []>;
976 def : WriteRes<WriteVST1, []>;
977 def : WriteRes<WriteVST2, []>;
978 def : WriteRes<WriteVST3, []>;
[all …]
H A DARMScheduleM55.td137 def : WriteRes<WriteBr, [M55UnitALU]>;
140 def : WriteRes<WriteST, [M55UnitALU]>;
221 def : WriteRes<WriteNoop, []>;
469 def : WriteRes<WriteVLD1, []>;
470 def : WriteRes<WriteVLD2, []>;
471 def : WriteRes<WriteVLD3, []>;
472 def : WriteRes<WriteVLD4, []>;
473 def : WriteRes<WriteVST1, []>;
474 def : WriteRes<WriteVST2, []>;
475 def : WriteRes<WriteVST3, []>;
[all …]
H A DARMScheduleR52.td74 def : WriteRes<WriteDIV, [R52UnitDiv]> {
79 def : WriteRes<WriteBr, [R52UnitB]> { let Latency = 0; }
108 def : WriteRes<WriteFPDIV32, [R52UnitDiv]> {
113 def : WriteRes<WriteFPDIV64, [R52UnitDiv]> {
122 def : WriteRes<WriteVST1, []>;
123 def : WriteRes<WriteVST2, []>;
124 def : WriteRes<WriteVST3, []>;
125 def : WriteRes<WriteVST4, []>;
719 def : WriteRes<WriteVLD2, [R52UnitLd]> {
725 def : WriteRes<WriteVLD3, [R52UnitLd]> {
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; }
65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; }
66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; }
67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
68 def : WriteRes<WriteALU, [ALU]> { let Latency = 1; }

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