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Searched refs:VALIGN (Results 1 – 11 of 11) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h112 VALIGN, // Align two vectors (in Op0, Op1) to one that would have enumerator
H A DHexagonISelLowering.cpp1939 case HexagonISD::VALIGN: return "HexagonISD::VALIGN"; in getTargetNodeName()
3232 SDValue Aligned = DAG.getNode(HexagonISD::VALIGN, dl, LoadTy, in LowerUnalignedLoad()
H A DHexagonISelDAGToDAG.cpp945 case HexagonISD::VALIGN: return SelectVAlign(N); in Select()
H A DHexagonISelLoweringHVX.cpp944 HalfV = DAG.getNode(HexagonISD::VALIGN, dl, VecTy, in buildHvxVectorReg()
H A DHexagonPatterns.td98 def HexagonVALIGN: SDNode<"HexagonISD::VALIGN", SDTVecVecIntOp>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedSapphireRapids.td664 "^VALIGN(D|Q)Z256rri((k|kz)?)$",
1364 "^VALIGN(D|Q)Z128rri((k|kz)?)$",
2032 "^VALIGN(D|Q)Z128rm(bi|ik)$",
2033 "^VALIGN(D|Q)Z128rmbik(z?)$",
2034 "^VALIGN(D|Q)Z128rmi((kz)?)$")>;
2654 def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instregex "^VALIGN(D|Q)Z((256)?)rm(bi|ik)$",
2655 "^VALIGN(D|Q)Z((256)?)rmbik(z?)$",
2656 "^VALIGN(D|Q)Z((256)?)rmi((kz)?)$",
H A DX86ISelLowering.h442 VALIGN, enumerator
H A DX86InstrFragmentsSIMD.td379 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
H A DX86SchedSkylakeServer.td1674 def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
H A DX86SchedIceLake.td1691 def: InstRW<[ICXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
H A DX86ISelLowering.cpp2616 case X86ISD::VALIGN: in isTargetShuffle()
5189 case X86ISD::VALIGN: in getTargetShuffleMask()
11384 return DAG.getNode(X86ISD::VALIGN, DL, VT, Lo, Hi, in lowerShuffleAsVALIGN()
11402 return DAG.getNode(X86ISD::VALIGN, DL, VT, Src, in lowerShuffleAsVALIGN()
11411 return DAG.getNode(X86ISD::VALIGN, DL, VT, in lowerShuffleAsVALIGN()
33300 NODE_NAME_CASE(VALIGN) in getTargetNodeName()
37587 Shuffle = X86ISD::VALIGN; in matchBinaryPermuteShuffle()
56268 case X86ISD::VALIGN: in PerformDAGCombine()