| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRedundantCopyElimination.cpp | 108 Register TargetReg = Cond[1].getReg(); in optimizeBlock() local
109 if (!TargetReg) in optimizeBlock()
124 TargetReg == DefReg) { in optimizeBlock()
136 if (MI->modifiesRegister(TargetReg, TRI)) in optimizeBlock()
147 assert(CondBr->getOperand(0).getReg() == TargetReg && "Unexpected register"); in optimizeBlock()
151 CondBr->clearRegisterKills(TargetReg, TRI); in optimizeBlock()
154 if (!MBB.isLiveIn(TargetReg)) in optimizeBlock()
155 MBB.addLiveIn(TargetReg); in optimizeBlock()
159 MMI.clearRegisterKills(TargetReg, TRI); in optimizeBlock()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 186 unsigned TargetReg = Inst.getOperand(1).getReg(); in emitInstruction() local
187 emitMask(TargetReg, IndirectBranchMaskReg, STI); in emitInstruction()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 991 unsigned TargetReg; in tracePredStateThroughIndirectBranches() local
1022 TargetReg = TI.getOperand(0).getReg(); in tracePredStateThroughIndirectBranches()
1042 TargetAddrSSA.AddAvailableValue(&MBB, TargetReg); in tracePredStateThroughIndirectBranches()
1109 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1114 TII->get(X86::MOV64ri32), TargetReg) in tracePredStateThroughIndirectBranches()
1122 TargetReg) in tracePredStateThroughIndirectBranches()
1134 TargetAddrSSA.AddAvailableValue(Pred, TargetReg); in tracePredStateThroughIndirectBranches()
1142 Register TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB); in tracePredStateThroughIndirectBranches() local
1153 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
1172 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
|
| H A D | X86ExpandPseudo.cpp | 229 auto TargetReg = STI->getTargetTriple().isOSWindows() ? X86::RCX : X86::RDI; in expandCALL_RVMARKER() local
231 .addReg(TargetReg, RegState::Define) in expandCALL_RVMARKER()
|
| H A D | X86ISelLowering.cpp | 57674 Register TargetReg; in EmitKCFICheck() local
57682 TargetReg = Target.getReg(); in EmitKCFICheck()
57691 TargetReg = X86::R11; in EmitKCFICheck()
57699 .addReg(TargetReg) in EmitKCFICheck()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.h | 174 Register TargetReg) const;
|
| H A D | AArch64FrameLowering.cpp | 743 Register TargetReg = RealignmentPadding in allocateStackSpace() local
754 .addReg(TargetReg, RegState::Kill) in allocateStackSpace()
833 Register TargetReg = findScratchNonCalleeSaveRegister(&MBB); in allocateStackSpace() local
834 assert(TargetReg != AArch64::NoRegister); in allocateStackSpace()
841 BuildMI(MBB, MBBI, DL, TII.get(AArch64::ANDXri), TargetReg) in allocateStackSpace()
842 .addReg(TargetReg, RegState::Kill) in allocateStackSpace()
848 .addReg(TargetReg); in allocateStackSpace()
4298 Register TargetReg) const { in inlineStackProbeLoopExactMultiple()
4326 .addReg(TargetReg) in inlineStackProbeLoopExactMultiple()
4453 Register TargetReg = MI->getOperand(0).getReg(); in inlineStackProbe() local
[all …]
|
| H A D | AArch64InstrInfo.h | 392 Register TargetReg,
|
| H A D | AArch64InstrInfo.cpp | 9512 Register TargetReg, bool FrameSetup) const { in probedStackAlloc() argument
9513 assert(TargetReg != AArch64::SP && "New top of stack cannot aleady be in SP"); in probedStackAlloc()
9543 .addReg(TargetReg) in probedStackAlloc()
9568 .addReg(TargetReg) in probedStackAlloc()
|
| H A D | AArch64ISelLowering.cpp | 2748 Register TargetReg = MI.getOperand(0).getReg(); in EmitDynamicProbedAlloc() local
2750 TII.probedStackAlloc(MBBI, TargetReg, false); in EmitDynamicProbedAlloc()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZAsmPrinter.cpp | 330 Register TargetReg = MI->getOperand(0).getReg(); in emitInstruction() local
341 if (TargetReg != ADAReg) { in emitInstruction()
342 IndexReg = TargetReg; in emitInstruction()
346 MCInstBuilder(SystemZ::LLILF).addReg(TargetReg).addImm(Disp)); in emitInstruction()
350 MCInstBuilder(SystemZ::ALGFI).addReg(TargetReg).addImm(Disp)); in emitInstruction()
355 .addReg(TargetReg) in emitInstruction()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 179 Register TargetReg) { in buildGitPtr() argument
184 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
185 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
190 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
193 BuildMI(MBB, I, DL, GetPC64, TargetReg); in buildGitPtr()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 866 Register TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
874 .addReg(TargetReg) in expandEhReturn()
877 .addReg(TargetReg) in expandEhReturn()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 3046 Register TargetReg = MI.getOperand(0).getReg(); in expandVSXMemPseudo() local
3048 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
3049 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
3133 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3134 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
3155 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3156 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 214 const SmallSet<Register, 2> &TargetReg,
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3644 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT() local
3649 {TargetReg, ScratchReg}, {JTAddr, Index}) in selectBrJT()
3655 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3209 Register TargetReg, Register InsertReg, in buildBitFieldInsert() argument
3211 LLT TargetTy = B.getMRI()->getType(TargetReg); in buildBitFieldInsert()
3225 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); in buildBitFieldInsert()
|