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Searched refs:Strided (Results 1 – 7 of 7) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h200 uint16_t Strided : 1; member
220 uint16_t Strided : 1; member
238 uint16_t Strided : 1; member
247 uint16_t Strided : 1; member
H A DRISCVInstrInfoVPseudos.td584 bits<1> Strided = Str;
606 bits<1> Strided = Str;
616 let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"];
653 bits<1> Strided = Str;
689 bits<1> Strided = Str;
917 RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
931 RISCVVSE</*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
945 RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
959 RISCVVSE</*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
6167 // 7.5 Vector Strided Instructions
[all …]
H A DRISCVScheduleV.td263 // 7.4.1. Vector Unit-Strided Mask
266 // 7.5. Vector Strided Instructions
517 // 7.4.1. Vector Unit-Strided Mask
519 // 7.5. Vector Strided Instructions
H A DRISCVInstrInfoV.td198 // Vector Strided Loads and Stores
261 // Strided Segment Loads and Stores
1060 // Vector Strided Instructions
1728 // Vector Strided Instructions
1770 // Vector Strided Segment Instructions
H A DRISCVSchedSiFive7.td460 // Strided loads and stores operate at one element per cycle and should be
565 // segment loads and stores. Strided segment loads and stores operate at up to
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td1698 // Strided loads/stores for fixed vectors.
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_vector.td697 // 7.5. Vector Strided Instructions