| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCDuplexInfo.cpp | 732 Result.setOpcode(Hexagon::SA1_addi); in deriveSubInst() 738 Result.setOpcode(Hexagon::SA1_addrx); in deriveSubInst() 749 Result.setOpcode(Hexagon::SA1_zxtb); in deriveSubInst() 754 Result.setOpcode(Hexagon::SA1_and1); in deriveSubInst() 955 Result.setOpcode(Hexagon::SA1_sxtb); in deriveSubInst() 960 Result.setOpcode(Hexagon::SA1_sxth); in deriveSubInst() 965 Result.setOpcode(Hexagon::SA1_tfr); in deriveSubInst() 980 Result.setOpcode(Hexagon::SA1_clrf); in deriveSubInst() 985 Result.setOpcode(Hexagon::SA1_clrt); in deriveSubInst() 1003 Result.setOpcode(Hexagon::SA1_zxtb); in deriveSubInst() [all …]
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| H A D | HexagonMCCompound.cpp | 214 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn() 227 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn() 241 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn() 254 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn() 267 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn() 285 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn() 303 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn() 314 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn() 325 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 286 Inst.setOpcode(XCore::ADD_3r); in Decode2OpInstructionFail() 289 Inst.setOpcode(XCore::SUB_3r); in Decode2OpInstructionFail() 292 Inst.setOpcode(XCore::SHL_3r); in Decode2OpInstructionFail() 295 Inst.setOpcode(XCore::SHR_3r); in Decode2OpInstructionFail() 298 Inst.setOpcode(XCore::EQ_3r); in Decode2OpInstructionFail() 301 Inst.setOpcode(XCore::AND_3r); in Decode2OpInstructionFail() 304 Inst.setOpcode(XCore::OR_3r); in Decode2OpInstructionFail() 307 Inst.setOpcode(XCore::LDW_3r); in Decode2OpInstructionFail() 313 Inst.setOpcode(XCore::LD8U_3r); in Decode2OpInstructionFail() 334 Inst.setOpcode(XCore::LSS_3r); in Decode2OpInstructionFail() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 249 T.setOpcode(Inst.getOpcode()); in ScaleVectorOffset() 278 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction() 292 Inst.setOpcode(Hexagon::A2_paddif); in HexagonProcessInstruction() 299 Inst.setOpcode(Hexagon::A2_paddit); in HexagonProcessInstruction() 306 Inst.setOpcode(Hexagon::A2_paddifnew); in HexagonProcessInstruction() 320 Inst.setOpcode(Hexagon::A2_andir); in HexagonProcessInstruction() 365 MappedInst.setOpcode(Hexagon::C2_or); in HexagonProcessInstruction() 421 Inst.setOpcode(Hexagon::J2_call); in HexagonProcessInstruction() 496 TmpInst.setOpcode(Hexagon::A2_tfr); in HexagonProcessInstruction() 610 TmpInst.setOpcode(Hexagon::V6_vxor); in HexagonProcessInstruction() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 165 MCB.setOpcode(Hexagon::BUNDLE); in HexagonAsmParser() 539 NewInst.setOpcode(MCI.getOpcode()); in canonicalizeImmediates() 1238 TmpInst.setOpcode(opCode); in makeCombineInst() 1345 Inst.setOpcode(Hexagon::A2_addi); in processInstruction() 1379 Inst.setOpcode(Hexagon::C2_cmpgti); in processInstruction() 1414 Inst.setOpcode(Hexagon::A2_combinew); in processInstruction() 1447 Inst.setOpcode(Hexagon::V6_vcombine); in processInstruction() 1689 Inst.setOpcode(Hexagon::M2_mpyi); in processInstruction() 1725 TmpInst.setOpcode(Hexagon::A2_tfr); in processInstruction() 1799 Inst.setOpcode(Hexagon::A2_addsph); in processInstruction() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 767 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction() 779 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction() 789 TmpInst.setOpcode(PPC::DCBTST); in ProcessInstruction() 812 TmpInst.setOpcode(PPC::DCBF); in ProcessInstruction() 821 TmpInst.setOpcode(PPC::LA); in ProcessInstruction() 830 TmpInst.setOpcode(PPC::ADDI); in ProcessInstruction() 839 TmpInst.setOpcode(PPC::ADDIS); in ProcessInstruction() 848 TmpInst.setOpcode(PPC::ADDIC); in ProcessInstruction() 857 TmpInst.setOpcode(PPC::ADDIC_rec); in ProcessInstruction() 1055 TmpInst.setOpcode(PPC::ADDPCIS); in ProcessInstruction() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 681 MI.setOpcode(Mips::BOVC); in DecodeAddiGroupBranch() 684 MI.setOpcode(Mips::BEQC); in DecodeAddiGroupBranch() 754 MI.setOpcode(Mips::BNVC); in DecodeDaddiGroupBranch() 757 MI.setOpcode(Mips::BNEC); in DecodeDaddiGroupBranch() 908 MI.setOpcode(Mips::BLEZC); in DecodeBlezlGroupBranch() 910 MI.setOpcode(Mips::BGEZC); in DecodeBlezlGroupBranch() 913 MI.setOpcode(Mips::BGEC); in DecodeBlezlGroupBranch() 956 MI.setOpcode(Mips::BLTC); in DecodeBgtzlGroupBranch() 994 MI.setOpcode(Mips::BGTZ); in DecodeBgtzGroupBranch() 1090 MI.setOpcode(Mips::DEXT); in DecodeDEXT() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEAsmPrinter.cpp | 86 SICInst.setOpcode(VE::SIC); in emitSIC() 94 BSICInst.setOpcode(VE::BSICrii); in emitBSIC() 106 LEAInst.setOpcode(VE::LEAzii); in emitLEAzzi() 118 LEASLInst.setOpcode(VE::LEASLzii); in emitLEASLzzi() 130 LEAInst.setOpcode(VE::LEAzii); in emitLEAzii() 143 LEASLInst.setOpcode(VE::LEASLrri); in emitLEASLrri() 155 Inst.setOpcode(Opcode); in emitBinary()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AsmPrinter.cpp | 1078 MI.setOpcode(Opcode); in LowerFAULTING_OP() 1107 MOVI.setOpcode(AArch64::MOVID); in emitFMov0() 1251 TmpInst.setOpcode(AArch64::BR); in emitInstruction() 1260 TmpInst.setOpcode(AArch64::B); in emitInstruction() 1280 TmpInstSB.setOpcode(AArch64::SB); in emitInstruction() 1302 Adrp.setOpcode(AArch64::ADRP); in emitInstruction() 1309 Ldr.setOpcode(AArch64::LDRWui); in emitInstruction() 1312 Ldr.setOpcode(AArch64::LDRXui); in emitInstruction() 1322 Add.setOpcode(AArch64::ADDWri); in emitInstruction() 1326 Add.setOpcode(AArch64::ADDXri); in emitInstruction() [all …]
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| H A D | AArch64MCInstLower.cpp | 303 OutMI.setOpcode(MI->getOpcode()); in Lower() 314 OutMI.setOpcode(AArch64::RET); in Lower() 319 OutMI.setOpcode(AArch64::RET); in Lower()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 2374 Inst.setOpcode(ARM::CPS3p); in DecodeCPSInstruction() 2379 Inst.setOpcode(ARM::CPS2p); in DecodeCPSInstruction() 2384 Inst.setOpcode(ARM::CPS1p); in DecodeCPSInstruction() 2389 Inst.setOpcode(ARM::CPS1p); in DecodeCPSInstruction() 2414 Inst.setOpcode(ARM::t2CPS3p); in DecodeT2CPSInstruction() 2419 Inst.setOpcode(ARM::t2CPS2p); in DecodeT2CPSInstruction() 2424 Inst.setOpcode(ARM::t2CPS1p); in DecodeT2CPSInstruction() 2432 Inst.setOpcode(ARM::t2HINT); in DecodeT2CPSInstruction() 2561 Inst.setOpcode(ARM::SETPAN); in DecodeSETPANInstruction() 2668 Inst.setOpcode(ARM::BLXi); in DecodeBranchImmInstruction() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVMCInstLower.cpp | 139 OutMI.setOpcode(RVV->BaseInstr); in lowerRISCVVMachineInstrToMCInst() 212 OutMI.setOpcode(MI->getOpcode()); in lowerRISCVMachineInstrToMCInst() 235 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst() 241 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 173 MI.setOpcode(Hexagon::BUNDLE); in getInstruction() 205 MI.setOpcode(Hexagon::S6_allocframe_to_raw); in remapInstruction() 213 MI.setOpcode(L6_deallocframe_map_to_raw); in remapInstruction() 221 MI.setOpcode(L6_return_map_to_raw); in remapInstruction() 229 MI.setOpcode(L4_return_map_to_raw_t); in remapInstruction() 237 MI.setOpcode(L4_return_map_to_raw_f); in remapInstruction() 245 MI.setOpcode(L4_return_map_to_raw_tnew_pt); in remapInstruction() 253 MI.setOpcode(L4_return_map_to_raw_fnew_pt); in remapInstruction() 261 MI.setOpcode(L4_return_map_to_raw_tnew_pnt); in remapInstruction() 269 MI.setOpcode(L4_return_map_to_raw_fnew_pnt); in remapInstruction() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 172 TmpInst.setOpcode(Opcode); in emitR() 181 TmpInst.setOpcode(Opcode); in emitRX() 201 TmpInst.setOpcode(Opcode); in emitII() 212 TmpInst.setOpcode(Opcode); in emitRRX() 230 TmpInst.setOpcode(Opcode); in emitRRRX() 250 TmpInst.setOpcode(Opcode); in emitRRIII() 1164 TmpInst.setOpcode(Mips::LUi); in emitDirectiveCpLoad() 1176 TmpInst.setOpcode(Mips::ADDiu); in emitDirectiveCpLoad() 1189 TmpInst.setOpcode(Mips::ADDu); in emitDirectiveCpLoad() 1292 Inst.setOpcode(Mips::OR); in emitDirectiveCpreturn() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 303 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions() 8681 TmpInst.setOpcode(Opcode); in processInstruction() 8719 TmpInst.setOpcode(Opcode); in processInstruction() 8737 TmpInst.setOpcode(ARM::ADR); in processInstruction() 9986 TmpInst.setOpcode(NewOpc); in processInstruction() 10021 TmpInst.setOpcode(newOpc); in processInstruction() 10074 TmpInst.setOpcode(newOpc); in processInstruction() 10136 TmpInst.setOpcode(Opc); in processInstruction() 10371 Inst.setOpcode(ARM::t2B); in processInstruction() 10378 Inst.setOpcode(ARM::tB); in processInstruction() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 123 TmpInst0.setOpcode(Mips::JALR64); in emitPseudoIndirectBranch() 128 TmpInst0.setOpcode(Mips::JRC16_MMR6); in emitPseudoIndirectBranch() 130 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch() 135 TmpInst0.setOpcode(Mips::JR_MM); in emitPseudoIndirectBranch() 138 TmpInst0.setOpcode(Mips::JR); in emitPseudoIndirectBranch() 860 I.setOpcode(Mips::JAL); in EmitJal() 869 I.setOpcode(Opcode); in EmitInstrReg() 888 I.setOpcode(Opcode); in EmitInstrRegReg() 898 I.setOpcode(Opcode); in EmitInstrRegRegReg()
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| H A D | MipsMCInstLower.cpp | 216 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi() 254 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu() 319 OutMI.setOpcode(MI->getOpcode()); in Lower()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.cpp | 38 NopInst.setOpcode(ARM::HINT); in getNop() 43 NopInst.setOpcode(ARM::MOVr); in getNop()
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| H A D | ARMAsmPrinter.cpp | 1445 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); in emitInstruction() 1476 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel in emitInstruction() 1803 TmpInst.setOpcode(Opc); in emitInstruction() 1818 TmpInst.setOpcode(ARM::LDRi12); in emitInstruction() 1831 TmpInst.setOpcode(ARM::LDRrs); in emitInstruction() 2185 TmpInstDSB.setOpcode(ARM::DSB); in emitInstruction() 2189 TmpInstISB.setOpcode(ARM::ISB); in emitInstruction() 2197 TmpInstDSB.setOpcode(ARM::t2DSB); in emitInstruction() 2203 TmpInstISB.setOpcode(ARM::t2ISB); in emitInstruction() 2213 TmpInstSB.setOpcode(ARM::SB); in emitInstruction() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 336 Inst.setOpcode(Opcode); in SimplifyShortImmForm() 364 Inst.setOpcode(NewOpcode); in SimplifyMOVSX() 415 Inst.setOpcode(Opcode); in SimplifyShortMoveForm() 525 OutMI.setOpcode(NewOpc); in Lower() 566 OutMI.setOpcode(NewOpc); in Lower() 580 OutMI.setOpcode(NewOpc); in Lower() 682 OutMI.setOpcode(NewOpc); in Lower() 1298 MI.setOpcode(Opcode); in LowerFAULTING_OP() 1336 MCI.setOpcode(Opcode); in LowerPATCHABLE_OP() 1712 Ret.setOpcode(OpCode); in LowerPATCHABLE_RET() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kMCInstLower.cpp | 147 OutMI.setOpcode(Opcode); in Lower() 168 OutMI.setOpcode(Opcode); in Lower()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUMCInstLower.cpp | 158 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64)); in lower() 177 OutMI.setOpcode(MCOpcode); in lower() 334 OutMI.setOpcode(MI->getOpcode()); in lower()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVAsmBackend.cpp | 177 Res.setOpcode(RISCV::BEQ); in relaxInstruction() 184 Res.setOpcode(RISCV::BNE); in relaxInstruction() 191 Res.setOpcode(RISCV::JAL); in relaxInstruction() 197 Res.setOpcode(RISCV::JAL); in relaxInstruction()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstBuilder.h | 27 Inst.setOpcode(Opcode); in MCInstBuilder()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMCInstLower.cpp | 48 OutMI.setOpcode(MI->getOpcode()); in Lower()
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