| /freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | DAGISelEmitter.cpp | 155 std::vector<const PatternToMatch*> Patterns; in run() local
157 Patterns.push_back(&PTM); in run()
161 llvm::stable_sort(Patterns, PatternSortingPredicate(CGP)); in run()
166 for (const PatternToMatch *PTM : Patterns) { in run()
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| H A D | AsmWriterEmitter.cpp | 1050 std::string Patterns; in EmitPrintAliasInstruction() local
1051 raw_string_ostream PatternO(Patterns); in EmitPrintAliasInstruction()
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| /freebsd-13.1/contrib/llvm-project/clang/lib/ASTMatchers/ |
| H A D | ASTMatchersInternal.cpp | 530 Patterns.reserve(Names.size()); in PatternSet()
532 Patterns.push_back({Name, Name.startswith("::")}); in PatternSet()
539 for (size_t I = 0; I < Patterns.size();) { in consumeNameSuffix()
545 Patterns.erase(Patterns.begin() + I); in consumeNameSuffix()
548 return !Patterns.empty(); in consumeNameSuffix()
567 llvm::SmallVector<Pattern, 8> Patterns; member in clang::ast_matchers::internal::__anonf6ae02b80811::PatternSet
582 PatternSet Patterns(Names); in matchesNodeFullFast() local
593 if (!Patterns.consumeNameSuffix(getNodeName(Node, Scratch), in matchesNodeFullFast()
602 return Patterns.foundMatch(/*AllowFullyQualified=*/false); in matchesNodeFullFast()
611 if (Patterns.foundMatch(/*AllowFullyQualified=*/false)) in matchesNodeFullFast()
[all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineCombiner.cpp | 125 SmallVector<MachineCombinerPattern, 16> &Patterns);
511 SmallVector<MachineCombinerPattern, 16> &Patterns) { in verifyPatternOrder() argument
514 for (auto P : Patterns) { in verifyPatternOrder()
565 SmallVector<MachineCombinerPattern, 16> Patterns; in combineInstructions() local
593 if (!TII->getMachineCombinerPatterns(MI, Patterns, DoRegPressureReduce)) in combineInstructions()
597 verifyPatternOrder(MBB, MI, Patterns); in combineInstructions()
599 for (auto P : Patterns) { in combineInstructions()
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| H A D | TargetInstrInfo.cpp | 778 MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns, in getMachineCombinerPatterns() argument
787 Patterns.push_back(MachineCombinerPattern::REASSOC_AX_YB); in getMachineCombinerPatterns()
788 Patterns.push_back(MachineCombinerPattern::REASSOC_XA_YB); in getMachineCombinerPatterns()
790 Patterns.push_back(MachineCombinerPattern::REASSOC_AX_BY); in getMachineCombinerPatterns()
791 Patterns.push_back(MachineCombinerPattern::REASSOC_XA_BY); in getMachineCombinerPatterns()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCInstPrinter.cpp | 137 ArrayRef<AliasPattern> Patterns = in matchAliasPatterns() local
138 M.Patterns.slice(It->PatternStart, It->NumPatterns); in matchAliasPatterns()
139 for (const AliasPattern &P : Patterns) { in matchAliasPatterns()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstPrinter.h | 182 ArrayRef<AliasPattern> Patterns; member
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | EXPInstructions.td | 94 // EXP Patterns
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| H A D | SIInstructions.td | 825 // VOP1 Patterns
909 // VOP2 Patterns
1586 /********** Immediate Patterns **********/
1670 /********** Intrinsic Patterns **********/
1708 // VOP3 Patterns
1841 // SAD Patterns
1860 // Conversion Patterns
2078 // Miscellaneous Patterns
2421 // Fract Patterns
2457 // Miscellaneous Optimization Patterns
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| H A D | AMDGPUGISel.td | 1 //===-- AMDGPUGIsel.td - AMDGPU GlobalISel Patterns---------*- tablegen -*-===//
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| H A D | R600Instructions.td | 1722 // ISel Patterns
1727 // CND*_INT Patterns for f32 True / False values
1744 // KIL Patterns
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrCompiler.td | 1 //===-- M68kInstrCompiler.td - Pseudos and Patterns ------*- tablegen -*-===//
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| H A D | M68kInstrControl.td | 272 // SETCC_C Patterns
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips64r6InstrInfo.td | 204 // Patterns and Pseudo Instructions
305 // Patterns used for matching away redundant sign extensions.
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| H A D | MicroMipsInstrFPU.td | 398 // Floating Point Patterns
401 // Patterns for loads/stores with a reg+imm operand.
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 248 SmallVectorImpl<MachineCombinerPattern> &Patterns,
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| H A D | AArch64InstrInfo.cpp | 4635 SmallVectorImpl<MachineCombinerPattern> &Patterns) { in getMaddPatterns() argument
4658 Patterns.push_back(Pattern); in getMaddPatterns()
4665 Patterns.push_back(Pattern); in getMaddPatterns()
4776 SmallVectorImpl<MachineCombinerPattern> &Patterns) { in getFMAPatterns() argument
4787 Patterns.push_back(Pattern); in getFMAPatterns()
5031 MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns, in getMachineCombinerPatterns() argument
5034 if (getMaddPatterns(Root, Patterns)) in getMachineCombinerPatterns()
5037 if (getFMAPatterns(Root, Patterns)) in getMachineCombinerPatterns()
5040 return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns, in getMachineCombinerPatterns()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrAtomics.td | 603 // Patterns for various addressing modes.
660 // Patterns for various addressing modes for truncating-extending binary RMWs.
839 // Patterns for various addressing modes.
896 // Patterns for various addressing modes for truncating-extending ternary RMWs.
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrVecCompiler.td | 1 //===- X86InstrVecCompiler.td - Vector Compiler Patterns ---*- tablegen -*-===//
56 // Patterns for insert_subvector/extract_subvector to/from index=0
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 368 MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns, in getFMAPatterns() argument
496 Patterns.push_back(MachineCombinerPattern::REASSOC_XY_BCA); in getFMAPatterns()
504 Patterns.push_back(MachineCombinerPattern::REASSOC_XY_BAC); in getFMAPatterns()
531 Patterns.push_back(MachineCombinerPattern::REASSOC_XMM_AMM_BMM); in getFMAPatterns()
536 Patterns.push_back(MachineCombinerPattern::REASSOC_XY_AMM_BMM); in getFMAPatterns()
760 MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns, in getMachineCombinerPatterns() argument
767 if (getFMAPatterns(Root, Patterns, DoRegPressureReduce)) in getMachineCombinerPatterns()
770 return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns, in getMachineCombinerPatterns()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/IPO/ |
| H A D | WholeProgramDevirt.cpp | 176 std::vector<GlobPattern> Patterns; member
180 Patterns.push_back(std::move(*Pat)); in init()
183 for (const GlobPattern &P : Patterns) in match()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 1 //===- HexagonPatterns.td - Selection Patterns for Hexagon -*- tablegen -*-===//
1975 // Patterns to select load-indexed: Rs + Off.
1986 // Patterns to select load-indexed: Rs + Off.
1997 // Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi.
2004 // Patterns to select load reg indexed: Rs + Off with a value modifier.
2015 // Patterns to select load reg indexed: Rs + Off with a value modifier.
2026 // Patterns to select load reg indexed: Rs + Off with a value modifier.
2335 // Patterns for loads of i1:
2356 // Patterns for generating stores, where the address takes different forms:
2387 // Patterns for generating stores, where the address takes different forms,
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| H A D | HexagonIntrinsics.td | 242 // Patterns for optimizing code generations for HVX.
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.td | 20 // Instruction Operands and Patterns
828 // Non-Instruction Patterns
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1118 SmallVectorImpl<MachineCombinerPattern> &Patterns,
|