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/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonMapAsm2IntrinV65.gen.td11 …sat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntReg…
12 …28B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntReg…
13 …sat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntReg…
21 …_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRe…
22 …h_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRe…
23 …_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRe…
24 …h_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRe…
39 …pabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntR…
41 …ahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, Double…
47 …_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRe…
[all …]
H A DHexagonDepMapAsm2Intrin.td1753 def: Pat<(int_hexagon_V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
1825 def: Pat<(int_hexagon_V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
1845 def: Pat<(int_hexagon_V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
1857 def: Pat<(int_hexagon_V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
2097 def: Pat<(int_hexagon_V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
2105 def: Pat<(int_hexagon_V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
2149 def: Pat<(int_hexagon_V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
2401 def: Pat<(int_hexagon_V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
2717 def: Pat<(int_hexagon_V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
2769 def: Pat<(int_hexagon_V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td40 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
41 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
43 HvxVR:$src3),
44 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
56 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
59 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
64 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
107 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
108 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
110 imm:$src3),
[all …]
H A DHexagonIntrinsics.td147 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
208 def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
209 (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>,
213 HvxVR:$src3),
214 (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>,
382 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3),
387 u3_0ImmPred:$src3),
407 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
408 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>,
412 IntRegs:$src3),
[all …]
H A DHexagonIntrinsicsV60.td208 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),
212 HvxVR:$src3),
213 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
217 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
221 HvxVR:$src3),
222 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
231 (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
254 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
255 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
259 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
[all …]
H A DHexagonIntrinsicsV5.td179 u2_0ImmPred:$src3),
180 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>;
185 IntRegs:$src3, u2_0ImmPred:$src4),
187 IntRegs:$src3, u2_0ImmPred:$src4)>;
H A DHexagonPseudo.td453 (ins PredRegs:$src1, HvxVR:$src2, HvxVR:$src3), V6_vcmov>,
456 (ins PredRegs:$src1, HvxWR:$src2, HvxWR:$src3), V6_vccombine>,
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrXOP.td175 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
182 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
270 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
302 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
310 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
318 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
333 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
349 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
357 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
364 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrFMA.td43 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
51 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
64 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
71 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
84 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
184 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
192 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
205 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
395 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
402 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrFragmentsSIMD.td798 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
804 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
810 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
815 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
820 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
825 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
831 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
837 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
1043 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1048 PatFrag<(ops node:$src1, node:$src2, node:$src3),
[all …]
H A DX86InstrShiftRotate.td696 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
703 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
710 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
717 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
724 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
731 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
770 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
776 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
783 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
789 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
H A DX86InstrSSE.td4117 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4126 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5793 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5803 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6393 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6402 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6420 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6429 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6509 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6518 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[all …]
H A DX86InstrAVX512.td1717 OpcodeStr, "$src3, $src2", "$src2, $src3",
1724 OpcodeStr, "$src3, $src2", "$src2, $src3",
1836 OpcodeStr, "$src3, $src2", "$src2, $src3",
1842 OpcodeStr, "$src3, $src2", "$src2, $src3",
6912 OpcodeStr, "$src3, $src2", "$src2, $src3",
6918 OpcodeStr, "$src3, $src2", "$src2, $src3",
6986 OpcodeStr, "$src3, $src2", "$src2, $src3",
6992 OpcodeStr, "$src3, $src2", "$src2, $src3",
7061 OpcodeStr, "$src3, $src2", "$src2, $src3",
12495 "$src3, $src2", "$src2, $src3",
[all …]
H A DX86InstrMMX.td116 (ins VR64:$src1, VR64:$src2, u8imm:$src3),
117 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
118 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>,
121 (ins VR64:$src1, i64mem:$src2, u8imm:$src3),
122 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
543 (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
544 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
546 GR32orGR64:$src2, imm:$src3))]>,
551 (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),
552 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td648 def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3),
666 def fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
667 (fma node:$src1, node:$src2, (fneg node:$src3))>;
671 def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
672 (fma node:$src2, node:$src3, node:$src1)>;
673 def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
674 (fma node:$src2, node:$src3, (fneg node:$src1))>;
677 def fnma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
678 (fneg (fma node:$src1, node:$src2, node:$src3))>;
679 def fnms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td470 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
471 "crc32 $dst, $src2, $src3",
474 GRRegs:$src3))]>;
513 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
514 "ladd $dst2, $dst1, $src1, $src2, $src3",
518 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
519 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
522 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
523 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
529 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td295 bits<8> src3;
306 let Inst{63-56} = src3;
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMInstrNEON.td1247 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
2016 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
2017 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
2295 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2332 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
4451 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4521 QPR:$src3,
4533 QPR:$src3,
4590 QPR:$src3,
4602 QPR:$src3,
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DREADME_P9.txt256 v ← bfp_MULTIPLY_ADD(src1, src3, src2)
261 v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
266 v ← bfp_MULTIPLY_ADD(src1,src3,src2)
271 v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
/freebsd-12.1/sys/gnu/dts/arm/
H A Dr8a7745-iwg22d-sodimm.dts206 playback = <&ssi3 &src3 &dvc0>;
H A Diwg20d-q7-common.dtsi231 playback = <&ssi1 &src3 &dvc1>;
H A Dr8a7778.dtsi278 src3: src-3 { }; label
655 "sru-src3", "sru-src4", "sru-src5",
/freebsd-12.1/contrib/gcc/
H A Dpostreload.c1332 rtx src3 = XEXP (SET_SRC (set), 1); in reload_cse_move2add() local
1333 HOST_WIDE_INT added_offset = INTVAL (src3); in reload_cse_move2add()
1348 < COSTS_N_INSNS (1) + rtx_cost (src3, SET)) in reload_cse_move2add()
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td2505 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2509 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
2512 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2516 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
2519 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2523 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
2526 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2530 "\t[$addr+$offset], {{$src1, $src2, $src3, $src4}};", []>;
2533 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2537 "\t[$addr+$offset], {{$src1, $src2, $src3, $src4}};", []>;
[all …]
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DGenericOpcodes.td486 // Behaves like llvm fma intrinsic ie src1 * src2 + src3
489 let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);

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