| /f-stack/dpdk/drivers/raw/ifpga/base/ |
| H A D | ifpga_fme_error.c | 54 writeq(val, &fme_err->fme_err); in fme_err_set_clear()
96 writeq(FME_PCIE0_ERROR_MASK, &fme_err->pcie0_err_mask); in fme_err_set_pcie0_errors()
102 writeq(pcie0_err.csr & FME_PCIE0_ERROR_MASK, in fme_err_set_pcie0_errors()
105 writeq(0UL, &fme_err->pcie0_err_mask); in fme_err_set_pcie0_errors()
139 writeq(pcie1_err.csr & FME_PCIE1_ERROR_MASK, in fme_err_set_pcie1_errors()
142 writeq(0UL, &fme_err->pcie1_err_mask); in fme_err_set_pcie1_errors()
204 writeq(ras_error_inj.csr, &fme_err->ras_error_inj); in fme_err_set_inject_errors()
217 writeq(0UL, &fme_err->pcie0_err_mask); in fme_error_enable()
218 writeq(0UL, &fme_err->pcie1_err_mask); in fme_error_enable()
219 writeq(0UL, &fme_err->ras_nonfat_mask); in fme_error_enable()
[all …]
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| H A D | ifpga_fme_pr.c | 27 writeq(fme_pr_error, &fme_pr->ccip_fme_pr_err); in pr_err_handle()
50 writeq(fme_pr_ctl.csr, &fme_pr->ccip_fme_pr_control); in fme_pr_write_init()
63 writeq(fme_pr_ctl.csr, &fme_pr->ccip_fme_pr_control); in fme_pr_write_init()
102 writeq(fme_pr_ctl.csr, &fme_pr->ccip_fme_pr_control); in fme_pr_write()
129 writeq(fme_pr_data.csr, in fme_pr_write()
162 writeq(fme_pr_ctl.csr, &fme_pr->ccip_fme_pr_control); in fme_pr_write_complete()
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| H A D | ifpga_feature_dev.c | 32 writeq(control.csr, &port_hdr->control); in __fpga_port_enable()
50 writeq(control.csr, &port_hdr->control); in __fpga_port_disable()
104 writeq(err_mask.csr, &port_err->error_mask); in port_err_mask()
153 writeq(mask.csr, &port_err->port_error); in port_err_clear()
156 writeq(first.csr, &port_err->port_first_error); in port_err_clear()
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| H A D | ifpga_fme_iperf.c | 60 writeq(ctl.csr, &iperf->ch_ctl); in fme_iperf_set_cache_freeze()
84 writeq(ctl.csr, &iperf->ch_ctl); in read_cache_counter()
151 writeq(ctl.csr, &iperf->vtd_ctl); in fme_iperf_set_vtd_freeze()
170 writeq(sip_ctl.csr, &iperf->vtd_sip_ctl); in read_iommu_sip_counter()
223 writeq(ctl.csr, &iperf->vtd_ctl); in read_iommu_counter()
287 writeq(ctl.csr, &iperf->fab_ctl); in read_fabric_counter()
369 writeq(ctl.csr, &iperf->fab_ctl); in fme_iperf_set_fab_port_enable()
401 writeq(ctl.csr, &iperf->fab_ctl); in fme_iperf_set_fab_freeze()
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| H A D | ifpga_port.c | 122 writeq(status.csr, &port_hdr->status); in port_set_ap1_event()
156 writeq(status.csr, &port_hdr->status); in port_set_ap2_event()
201 writeq(val, &port_hdr->user_clk_freq_cmd0); in port_set_userclk_freqcmd()
229 writeq(val, &port_hdr->user_clk_freq_cmd1); in port_set_userclk_freqcntrcmd()
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| H A D | ifpga_fme_dperf.c | 68 writeq(ctl.csr, &dperf->fab_ctl); in read_fabric_counter()
146 writeq(ctl.csr, &dperf->fab_ctl); in fme_dperf_set_fab_port_enable()
178 writeq(ctl.csr, &dperf->fab_ctl); in fme_dperf_set_fab_freeze()
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| H A D | ifpga_compat.h | 28 #define writeq(value, addr) opae_writeq(value, addr) macro
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| H A D | ifpga_fme.c | 236 writeq(tmp_threshold.csr, &thermal->threshold); in fme_thermal_set_threshold1()
285 writeq(tmp_threshold.csr, &thermal->threshold); in fme_thermal_set_threshold2()
372 writeq(tmp_threshold.csr, &thermal->threshold); in fme_thermal_set_threshold1_policy()
539 writeq(pm_ap_threshold.csr, &fme_power->threshold); in fme_pwr_set_threshold1()
576 writeq(pm_ap_threshold.csr, &fme_power->threshold); in fme_pwr_set_threshold2()
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| /f-stack/dpdk/drivers/bus/fslmc/mc/ |
| H A D | fsl_mc_sys.h | 25 #define iowrite64(_v, _p) writeq(_v, _p)
44 #define writeq(v, c) \ macro
49 #define iowrite64(_v, _p) writeq(_v, _p)
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| /f-stack/dpdk/drivers/net/enic/base/ |
| H A D | vnic_cq.c | 52 writeq(paddr, &cq->ctrl->ring_base); in vnic_cq_init()
63 writeq(cq_message_addr, &cq->ctrl->cq_message_addr); in vnic_cq_init()
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| H A D | vnic_rq.c | 54 writeq(paddr, &rq->ctrl->ring_base); in vnic_rq_init_start()
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| H A D | vnic_wq.c | 96 writeq(paddr, &wq->ctrl->ring_base); in vnic_wq_init_start()
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| H A D | vnic_dev.h | 29 static inline void writeq(uint64_t val, void __iomem *reg) in writeq() function
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| H A D | vnic_dev.c | 328 writeq(vdev->args[i], &devcmd->args[i]); in _vnic_dev_cmd()
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| /f-stack/dpdk/drivers/net/ionic/ |
| H A D | ionic_osdep.h | 56 #define writeq(value, reg) rte_write64(value, reg) macro
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| H A D | ionic_regs.h | 139 writeq(val, &db_page[qtype]); in ionic_dbell_ring()
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| H A D | ionic_dev.c | 464 writeq(IONIC_DBELL_QID(q->hw_index) | q->head_idx, q->db); in ionic_q_flush()
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| /f-stack/dpdk/drivers/common/iavf/ |
| H A D | iavf_osdep.h | 105 writeq(uint64_t value, volatile void *addr) in writeq() function
112 #define wr64(a, reg, value) writeq((value), (a)->hw_addr + (reg))
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| /f-stack/dpdk/drivers/net/ice/base/ |
| H A D | ice_osdep.h | 113 writeq(uint64_t value, volatile void *addr) in writeq() function
120 #define wr64(a, reg, value) writeq((value), (a)->hw_addr + (reg))
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| /f-stack/dpdk/drivers/net/cxgbe/ |
| H A D | cxgbe_compat.h | 237 static inline void writeq(u64 val, volatile void __iomem *addr) in writeq() function
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| /f-stack/freebsd/mips/mips/ |
| H A D | bus_space_generic.c | 215 #ifdef writeq
216 #define wr64(a, v) writeq(a, v)
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| /f-stack/freebsd/mips/include/ |
| H A D | cpufunc.h | 387 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d)) macro
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| /f-stack/freebsd/amd64/include/ |
| H A D | cpufunc.h | 58 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d)) macro
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