Searched refs:tweaks (Results 1 – 5 of 5) sorted by relevance
331 __m128i tweaks[8]; in aesni_crypt_xts_block8() local345 tweaks[(pos)] = tmptweak; \ in aesni_crypt_xts_block8()368 _mm_storeu_si128(&top[0], tmp[0] ^ tweaks[0]); in aesni_crypt_xts_block8()369 _mm_storeu_si128(&top[1], tmp[1] ^ tweaks[1]); in aesni_crypt_xts_block8()370 _mm_storeu_si128(&top[2], tmp[2] ^ tweaks[2]); in aesni_crypt_xts_block8()371 _mm_storeu_si128(&top[3], tmp[3] ^ tweaks[3]); in aesni_crypt_xts_block8()372 _mm_storeu_si128(&top[4], tmp[4] ^ tweaks[4]); in aesni_crypt_xts_block8()373 _mm_storeu_si128(&top[5], tmp[5] ^ tweaks[5]); in aesni_crypt_xts_block8()374 _mm_storeu_si128(&top[6], tmp[6] ^ tweaks[6]); in aesni_crypt_xts_block8()375 _mm_storeu_si128(&top[7], tmp[7] ^ tweaks[7]); in aesni_crypt_xts_block8()
16 SiFive PWM v0 IP block with no chip integration tweaks.
7 or 2500 family SoC as they have some subtle tweaks to the
28 SPI v0 IP block with no chip integration tweaks.
34 CLINT v0 IP block with no chip integration tweaks.