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/f-stack/freebsd/contrib/device-tree/Bindings/reset/
H A Dzynq-reset.txt25 0 : soft reset
26 32 : ddr reset
28 96 : dmac reset
29 128: usb0 reset
30 129: usb1 reset
31 160: gem0 reset
32 161: gem1 reset
41 224: spi0 reset
42 225: spi1 reset
58 416: smc reset
[all …]
H A Dsocionext,uniphier-reset.yaml4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
7 title: UniPhier reset controller
15 - description: System reset
26 - description: Media I/O (MIO) reset, SD reset
52 "#reset-cells":
59 - "#reset-cells"
67 reset {
69 #reset-cells = <1>;
80 reset {
93 reset {
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H A Dreset.txt10 reset consumer (the module being reset, or a module managing when a sub-
14 A reset signal is represented by the phandle of the provider, plus a reset
24 may be reset. Instead, reset signals should be represented in the DT node
35 #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
37 reset outputs.
41 rst: reset-controller {
42 #reset-cells = <1>;
55 reset-names: List of reset signal name strings sorted in the same order as
57 match reset signal names with reset specifiers.
63 reset-names = "reset";
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H A Dsnps,hsdk-reset.txt1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
21 Specifying reset lines connected to IP modules:
24 resets = <&reset HSDK_V1_ETH_RESET>;
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H A Dfsl,imx7-src.txt4 Please also refer to reset.txt in this directory for common reset
17 - #reset-cells: 1, see below
21 src: reset-controller@30390000 {
25 #reset-cells = <1>;
32 The system reset controller can be used to reset various set of
35 specified in reset.txt.
52 <dt-bindings/reset/imx7-reset.h> for i.MX7,
53 <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and
54 <dt-bindings/reset/imx8mq-reset.h> for i.MX8MM and
55 <dt-bindings/reset/imx8mq-reset.h> for i.MX8MN and
[all …]
H A Dti-syscon-reset.txt27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
35 Cell #2 : bit position of the reset in the reset
39 Cell #4 : bit position of the reset in the reset
44 reset status register
57 to a reset specifier as defined above.
59 Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
74 pscrst: reset-controller {
76 #reset-cells = <1>;
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H A Dsnps,axs10x-reset.txt1 Binding for the AXS10x reset controller
6 represents up-to 32 reset lines.
11 This binding uses the common reset binding[1].
13 [1] Documentation/devicetree/bindings/reset/reset.txt
16 - compatible: should be "snps,axs10x-reset".
19 - #reset-cells: from common reset binding; Should always be set to 1.
22 reset: reset-controller@11220 {
23 compatible = "snps,axs10x-reset";
24 #reset-cells = <1>;
28 Specifying reset lines connected to IP modules:
[all …]
H A Dxlnx,zynqmp-reset.txt2 = Zynq UltraScale+ MPSoC reset driver binding =
9 Please also refer to reset.txt in this directory for common reset
13 - compatible: "xlnx,zynqmp-reset"
14 - #reset-cells: Specifies the number of cells needed to encode reset
26 zynqmp_reset: reset-controller {
27 compatible = "xlnx,zynqmp-reset";
28 #reset-cells = <1>;
38 specified in reset.txt.
40 For list of all valid reset indicies see
41 <dt-bindings/reset/xlnx-zynqmp-resets.h>
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H A Dimg,pistachio-reset.txt13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
33 #reset-cells = <1>;
37 Specifying reset control of devices
43 Documentation/devicetree/bindings/reset/reset.txt.
50 reset-names = "rst";
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H A Dbrcm,brcmstb-reset.txt1 Broadcom STB SW_INIT-style reset controller
4 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
6 reset lines.
8 Please also refer to reset.txt in this directory for common reset
12 - compatible: should be brcm,brcmstb-reset
14 - #reset-cells: must be set to 1
18 reset: reset-controller@8404318 {
19 compatible = "brcm,brcmstb-reset";
21 #reset-cells = <1>;
25 resets = <&reset 26>;
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H A Dfsl,imx7-src.yaml4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
13 The system reset controller can be used to reset various set of
16 specified in reset.txt.
18 For list of all valid reset indices see
19 <dt-bindings/reset/imx7-reset.h> for i.MX7,
20 <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,
21 <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP.
38 '#reset-cells':
45 - '#reset-cells'
53 reset-controller@30390000 {
[all …]
H A Duniphier-reset.txt1 UniPhier glue reset controller
4 Peripheral core reset in glue layer
13 "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
14 "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
15 "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
21 - #reset-cells: Should be 1.
30 - reset-names: Should contain
43 usb_rst: reset@0 {
44 compatible = "socionext,uniphier-ld20-usb3-reset";
46 #reset-cells = <1>;
[all …]
H A Dallwinner,sun6i-a31-clock-reset.yaml4 $id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml#
20 - allwinner,sun6i-a31-ahb1-reset
21 - allwinner,sun6i-a31-clock-reset
31 "#reset-cells":
40 - allwinner,sun6i-a31-ahb1-reset
41 - allwinner,sun6i-a31-clock-reset
47 - "#reset-cells"
55 ahb1_rst: reset@1c202c0 {
56 #reset-cells = <1>;
62 apbs_rst: reset@80014b0 {
[all …]
H A Dnuvoton,npcm-reset.txt4 - compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
6 - #reset-cells: must be set to 2
9 - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
10 NPCM7xx contain four software reset that represent numbers 1 to 4.
12 If 'nuvoton,sw-reset-number' is not specfied software reset is disabled.
16 compatible = "nuvoton,npcm750-reset";
18 #reset-cells = <2>;
19 nuvoton,sw-reset-number = <2>;
22 Specifying reset lines connected to IP NPCM7XX modules
32 The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
H A Dhisilicon,hi3660-reset.txt4 Please also refer to reset.txt in this directory for common reset
7 The reset controller registers are part of the system-ctl block on
12 "hisilicon,hi3660-reset" for HI3660
13 "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670
14 - hisi,rst-syscon: phandle of the reset's syscon.
15 - #reset-cells : Specifies the number of cells needed to encode a
18 Cell #1 : offset of the reset assert control
22 Cell #2 : bit position of the reset in the reset control register
31 compatible = "hisilicon,hi3660-reset";
33 #reset-cells = <2>;
[all …]
H A Dlantiq,reset.txt1 Lantiq XWAY SoC RCU reset controller binding
12 "lantiq,danube-reset"
13 "lantiq,xrx200-reset"
16 - Offset of the reset set register
17 - Offset of the reset status register
19 reset line, should be 2.
20 The first cell takes the reset set bit and the
24 Example for the reset-controllers on the xRX200 SoCs:
25 reset0: reset-controller@10 {
26 compatible = "lantiq,xrx200-reset";
[all …]
H A Dath79-reset.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller
3 Please also refer to reset.txt in this directory for common reset
7 - compatible: has to be "qca,<soctype>-reset", "qca,ar7100-reset"
10 - #reset-cells : Specifies the number of cells needed to encode reset
15 reset-controller@1806001c {
16 compatible = "qca,ar9132-reset", "qca,ar7100-reset";
19 #reset-cells = <1>;
H A Dintel,rcu-gw.yaml4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
22 intel,global-reset:
31 "#reset-cells":
35 First cell is reset request register offset.
37 Third cell is bit offset in reset status register.
39 reset request and reset status registers is same. Whereas
45 - intel,global-reset
46 - "#reset-cells"
52 rcu0: reset-controller@e0000000 {
55 intel,global-reset = <0x10 30>;
[all …]
H A Dsnps,dw-reset.txt4 Please also refer to reset.txt in this directory for common reset
10 "snps,dw-high-reset" - for active high configuration
11 "snps,dw-low-reset" - for active low configuration
16 - #reset-cells: must be 1.
20 dw_rst_1: reset-controller@0000 {
21 compatible = "snps,dw-high-reset";
23 #reset-cells = <1>;
26 dw_rst_2: reset-controller@1000 {i
27 compatible = "snps,dw-low-reset";
29 #reset-cells = <1>;
H A Damlogic,meson-reset.yaml5 $id: "http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#"
16 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
17 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
19 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
24 "#reset-cells":
30 - "#reset-cells"
36 reset-controller@c884404 {
37 compatible = "amlogic,meson-gxbb-reset";
39 #reset-cells = <1>;
H A Dberlin,reset.txt1 Marvell Berlin reset controller
4 Please also refer to reset.txt in this directory for common reset
7 The reset controller node must be a sub-node of the chip controller
11 - compatible: should be "marvell,berlin2-reset"
12 - #reset-cells: must be set to 2
16 chip_rst: reset {
17 compatible = "marvell,berlin2-reset";
18 #reset-cells = <2>;
H A Dti,sci-reset.txt14 This reset controller node uses the TI SCI protocol to perform the reset
20 - compatible : Should be "ti,sci-reset"
21 - #reset-cells : Should be 2. Please see the reset consumer node below for
31 - resets : A phandle and reset specifier pair, one pair for each reset
34 and the reset specifier should have 2 cell-values. The first
36 contain the reset mask value used by system controller.
41 Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
42 common reset controller usage by consumers.
52 k2g_reset: reset-controller {
53 compatible = "ti,sci-reset";
[all …]
H A Doxnas,reset.txt4 Please also refer to reset.txt in this directory for common reset
8 - compatible: For OX810SE, should be "oxsemi,ox810se-reset"
9 For OX820, should be "oxsemi,ox820-reset"
10 - #reset-cells: 1, see below
19 - For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h
20 - For OX820: include/dt-bindings/reset/oxsemi,ox820.h
28 reset: reset-controller {
29 compatible = "oxsemi,ox810se-reset";
30 #reset-cells = <1>;
/f-stack/freebsd/contrib/device-tree/Bindings/power/reset/
H A Dkeystone-reset.txt3 This node is intended to allow SoC reset in case of software reset
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
37 Setup keystone reset so that in case software reset or
50 rstctrl: reset-controller {
51 compatible = "ti,keystone-reset";
58 Setup keystone reset so that in case of software reset or
61 rstctrl: reset-controller {
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/power/
H A Damlogic,meson-gx-pwrc.txt25 as described in ../reset/reset.txt
46 <&reset RESET_VENC>,
47 <&reset RESET_VCBUS>,
48 <&reset RESET_BT656>,
50 <&reset RESET_RDMA>,
51 <&reset RESET_VENCI>,
52 <&reset RESET_VENCP>,
53 <&reset RESET_VDAC>,
54 <&reset RESET_VDI6>,
55 <&reset RESET_VENCL>,
[all …]

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