| /f-stack/freebsd/contrib/device-tree/Bindings/mfd/ |
| H A D | mc13xxx.txt | 55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
86 sw1 : regulator SW1 (register 24, bit 0)
87 sw2 : regulator SW2 (register 25, bit 0)
88 sw3 : regulator SW3 (register 26, bit 0)
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| /f-stack/freebsd/contrib/device-tree/Bindings/leds/ |
| H A D | register-bit-led.txt | 4 where single bits in a certain register can turn on/off a
16 - compatible : must be "register-bit-led"
17 - offset : register offset to the register controlling this LED
36 compatible = "register-bit-led";
44 compatible = "register-bit-led";
52 compatible = "register-bit-led";
60 compatible = "register-bit-led";
67 compatible = "register-bit-led";
74 compatible = "register-bit-led";
81 compatible = "register-bit-led";
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| /f-stack/freebsd/contrib/device-tree/src/mips/mti/ |
| H A D | sead3.dts | 114 compatible = "register-bit-led";
120 compatible = "register-bit-led";
126 compatible = "register-bit-led";
132 compatible = "register-bit-led";
138 compatible = "register-bit-led";
144 compatible = "register-bit-led";
150 compatible = "register-bit-led";
156 compatible = "register-bit-led";
163 compatible = "register-bit-led";
169 compatible = "register-bit-led";
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| /f-stack/freebsd/contrib/device-tree/Bindings/power/reset/ |
| H A D | syscon-poweroff.yaml | 7 title: Generic SYSCON mapped register poweroff driver
13 This is a generic poweroff driver using syscon to map the poweroff register.
14 The poweroff is generally performed with a write to the poweroff register
15 defined by the register map pointed by syscon reference plus the offset
25 description: Update only the register bits defined by the mask (32 bit).
29 description: Offset in the register map for the poweroff register (in bytes).
33 description: Phandle to the register map node.
37 description: The poweroff value written to the poweroff register (32 bit access).
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| H A D | syscon-reboot.yaml | 7 title: Generic SYSCON mapped register reset driver
13 This is a generic reset driver using syscon to map the reset register.
14 The reset is generally performed with a write to the reset register
15 defined by the SYSCON register map base plus the offset with the value and
28 description: Update only the register bits defined by the mask (32 bit).
32 description: Offset in the register map for the reboot register (in bytes).
38 Phandle to the register map node. This property is deprecated in favor of
43 description: The reset value written to the reboot register (32 bit access).
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| H A D | syscon-reboot-mode.yaml | 14 and stores it in a SYSCON mapped register. Then the bootloader
16 value stored. The SYSCON mapped register is retrieved from the
26 description: Update only the register bits defined by the mask (32 bit)
30 description: Offset in the register map for the mode register (in bytes)
35 description: Vendor-specific mode value written to the mode register
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| /f-stack/freebsd/contrib/device-tree/Bindings/reset/ |
| H A D | ti-syscon-reset.txt | 7 sometimes a part of a larger register space region implementing various
8 functionalities. This register range is best represented as a syscon node to
10 register space.
30 - ti,reset-bits : Contains the reset control register information
34 register from the syscon register base
36 assert control register
38 register from the syscon register base
40 deassert control register
41 Cell #5 : offset of the reset status register
42 from the syscon register base
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| H A D | hisilicon,hi3660-reset.txt | 19 register from the syscon register base
20 offset + 4: deassert control register
21 offset + 8: status control register
22 Cell #2 : bit position of the reset in the reset control register
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| /f-stack/freebsd/contrib/device-tree/Bindings/pinctrl/ |
| H A D | pinctrl-single.txt | 1 One-register-per-pin type device tree based pinctrl driver
13 - pinctrl-single,register-width : pinmux register access width in bits
16 in the pinmux register
35 input bias pullup in the pinmux register.
41 input bias pulldown in the pinmux register.
115 be used when applying this change to the register.
143 pinctrl-single,register-width = <16>;
155 pinctrl-single,register-width = <16>;
161 reg = <0x48002274 4>; /* Single register */
165 pinctrl-single,register-width = <32>;
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| /f-stack/freebsd/contrib/device-tree/Bindings/c6x/ |
| H A D | dscr.txt | 9 more configuration registers often protected by a lock register where one or
10 more key values must be written to a lock register in order to unlock the
11 configuration register for writes. These configuration register may be used to
13 sources (internal or pin), etc. In some cases, a configuration register is
25 - reg: register area base and size
35 offset of the devstat register
46 a lock register. Each tuple consists of the register offset, lock register
47 offsset, and the key value used to unlock the register.
58 a register offset and four cells representing bytes in the register from
73 reg is the offset of the register holding the control bits
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| /f-stack/freebsd/contrib/device-tree/Bindings/clock/ti/ |
| H A D | mux.txt | 6 register-mapped multiplexer with multiple input clock signals or
15 results in programming the register as follows:
17 register value selected parent clock
23 into the register, instead indexing begins at 1. The optional property
26 register value selected clock parent
31 The binding must provide the register to control the mux. Optionally
32 the number of bits to shift the control field in the register can be
42 - reg : register offset for register controlling adjustable mux
51 - ti,latch-bit : latch the mux value to HW, only needed if the register
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| /f-stack/freebsd/contrib/device-tree/Bindings/mmc/ |
| H A D | sdhci.txt | 7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8 property corresponds to the bits in the sdhci capability register. If the bit
9 is on in the mask then the bit is incorrect in the register and should be
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
12 property corresponds to the bits in the sdhci capability register. If the
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| H A D | sdhci-msm.txt | 28 - reg: Base address and length of the register in the following order:
29 - Host controller register map (required)
30 - SD Core register map (required for controllers earlier than msm-v5)
31 - CQE register map (Optional, CQE support is present on SDHC instance meant
33 - reg-names: When CQE register map is supplied, below reg-names are required
34 - "hc" for Host controller register map
35 - "core" for SD core register map
36 - "cqhci" for CQE register map
51 for the DDR_CONFIG register. Use this field to specify the register
55 specify the DLL_CONFIG register value as per Hardware Programming Guide.
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| /f-stack/freebsd/contrib/device-tree/Bindings/phy/ |
| H A D | ti-phy.txt | 7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
39 - reg : Address and length of the register set for the device.
54 module and the register offset to power on/off the PHY.
72 - reg : Address and length of the register set for the device.
93 CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
96 register offset to write the PCS delay value.
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| /f-stack/freebsd/contrib/device-tree/Bindings/rtc/ |
| H A D | rtc-meson-vrtc.txt | 4 virtual from a Linux perspective. The interface is 1 register where
9 - reg: physical address for the alarm register
11 The alarm register is a simple scratch register shared between the
13 the AP suspends, the SCP will use the value of this register to
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| /f-stack/freebsd/contrib/device-tree/Bindings/net/ |
| H A D | micrel.txt | 12 KSZ8001: register 0x1e, bits 15..14
13 KSZ8041: register 0x1e, bits 15..14
14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
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| /f-stack/freebsd/contrib/device-tree/Bindings/i2c/ |
| H A D | i2c-mux-reg.txt | 3 This binding describes an I2C bus multiplexer that uses a single register
14 - reg: this pair of <offset size> specifies the register to control the mux.
18 - little-endian: The existence indicates the register is in little endian.
19 - big-endian: The existence indicates the register is in big endian.
22 - write-only: The existence indicates the register is write-only.
27 in the relevant node's reg property will be output to the register.
31 register will be set according to the idle value.
34 left programmed into the register.
45 little-endian; /* little endian register on PCIe */
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| /f-stack/freebsd/contrib/device-tree/Bindings/leds/backlight/ |
| H A D | arcxcnn_bl.txt | 14 - arc,led-config-0: setting for register ILED_CONFIG_0
15 - arc,led-config-1: setting for register ILED_CONFIG_1
17 - arc,comp-config: setting for register CONFIG_COMP
18 - arc,filter-config: setting for register FILTER_CONFIG
19 - arc,trim-config: setting for register IMAXTUNE
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| /f-stack/freebsd/contrib/device-tree/Bindings/serial/ |
| H A D | fsl-lpuart.txt | 6 on Vybrid vf610 SoC with 8-bit register organization
8 on LS1021A SoC with 32-bit big-endian register organization
10 on LS1028A SoC with 32-bit little-endian register organization
12 on i.MX7ULP SoC with 32-bit little-endian register organization
14 on i.MX8QXP SoC with 32-bit little-endian register organization
16 on i.MX8QM SoC with 32-bit little-endian register organization
17 - reg : Address and length of the register set for the device
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| /f-stack/freebsd/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | renesas,intc-irqpin.yaml | 25 - description: Interrupt control register
26 - description: Interrupt priority register
27 - description: Interrupt source register
28 - description: Interrupt mask register
29 - description: Interrupt mask clear register
30 - description: Interrupt control register for ICR0 with IRLM0 bit
46 Width of a single sense bitfield in the SENSE register, if different from the
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| /f-stack/freebsd/contrib/device-tree/Bindings/sound/ |
| H A D | alc5623.txt | 10 - add-ctrl: Default register value for Reg-40h, Additional Control
12 register is untouched.
14 - jack-det-ctrl: Default register value for Reg-5Ah, Jack Detect
16 register is untouched.
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| /f-stack/freebsd/contrib/device-tree/Bindings/misc/ |
| H A D | nvidia,tegra186-misc.txt | 1 NVIDIA Tegra186 MISC register block
3 The MISC register block found on Tegra186 SoCs contains registers that can be
10 and length of the register region which contains revision and debug
12 of the register region indicating the strapping options.
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| /f-stack/freebsd/contrib/device-tree/Bindings/clock/ |
| H A D | qcom,lpasscc.txt | 7 - reg : shall contain base register address and size,
9 Index-0 maps to LPASS_CC register region
10 Index-1 maps to LPASS_QDSP6SS register region
13 - reg-names : register names of LPASS domain
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| /f-stack/freebsd/contrib/device-tree/Bindings/arm/ |
| H A D | fw-cfg.txt | 7 - A write-only, 16-bit wide selector (or control) register,
8 - a read-write, 64-bit wide data register.
10 QEMU exposes the control and data register to ARM guests as memory mapped
23 * Bytes 0x0 to 0x7 cover the data register.
24 * Bytes 0x8 to 0x9 cover the selector register.
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| /f-stack/freebsd/contrib/device-tree/Bindings/gpu/ |
| H A D | brcm,bcm-v3d.txt | 8 - reg: Physical base addresses and lengths of the register areas
9 - reg-names: Names for the register areas. The "hub" and "core0"
10 register areas are always required. The "gca" register area
12 "bridge" register area is required if an external reset
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