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/f-stack/freebsd/crypto/openssl/arm/
H A Dghashv8-armx.S32 vext.8 q8,q12,q12,#8 @ Karatsuba pre-processing
38 vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
53 vext.8 q9,q14,q14,#8 @ Karatsuba pre-processing
73 veor q9,q9,q3 @ Karatsuba pre-processing
77 vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
141 veor q9,q9,q7 @ Karatsuba pre-processing
153 veor q10,q10,q3 @ Karatsuba pre-processing
163 vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
187 veor q9,q9,q7 @ Karatsuba pre-processing
203 veor q9,q9,q3 @ Karatsuba pre-processing
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/f-stack/freebsd/contrib/device-tree/Bindings/firmware/
H A Dintel,ixp4xx-network-processing-engine.yaml5 $id: "http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#"
25 - const: intel,ixp4xx-network-processing-engine
42 compatible = "intel,ixp4xx-network-processing-engine";
/f-stack/dpdk/doc/guides/prog_guide/
H A Drte_security.rst44 The crypto processing for security protocol (e.g. IPsec) is processed
50 crypto processing the packet is presented to host as a regular Rx packet
115 The crypto and protocol processing for security protocol (e.g. IPsec)
129 This will allow the application to identify the security processing
144 The hardware device will do security processing on the packet that includes
155 processing. E.g. in case of IPsec, the seq number will be added to the
197 the definition. In addition to standard crypto processing, as defined by
198 the cryptodev, the security protocol processing is also offloaded to the
202 protocol processing. The device will decrypt the packet and it will also
238 | | Crypto | | | <- Crypto processing through
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H A Dipsec_lib.rst7 DPDK provides a library for IPsec data-path processing.
10 high performant IPsec packet processing API.
11 The library is concentrated on data-path protocols processing
36 The expected API call sequence for data-path processing would be:
40 /* enqueue for processing by crypto-device */
43 /* dequeue from crypto-device and do final processing (if any) */
48 For packets destined for inline processing no extra overhead
113 inline-crypto processing has to be performed by HW on this packet
130 inline-crypto processing has to be performed by HW on this packet
H A Dpacket_distrib_lib.rst26 The distributor core does the majority of the processing for ensuring that packets are fairly share…
39 then that packet will be queued up for processing by that worker
45 or been queued up for a worker which is processing a given tag,
58 It returns to the caller all packets which have finished processing by all worker cores.
88 …istributor_get_pkt()" API to request a new packet when it has finished processing the previous one.
93 it is possible to have a worker stop processing packets by calling "rte_distributor_return_pkt()" t…
H A Dcompressdev.rst98 A queue pair cannot be shared and should be exclusively used by a single processing
104 data processing pipeline.
178 ranks for optimal processing.
196 mbuf-chain and enqueue it for processing or, alternatively, it can
198 processing them statefully. See *Compression API Stateful Operation*
199 for stateful processing of ops.
222 Output buffer ran out of space during processing. Error case,
298 When all of the above conditions are met, PMD initiates stateless processing
299 and releases acquired resources after processing of current operation is
438 stateful processing and releases acquired resources after processing
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H A Dmetrics_lib.rst240 processing by a DPDK application, reporting the minimum, average,
241 and maximum nano-seconds that packet processing takes, as well as
242 the jitter in processing delay. These statistics are then reported
245 - ``min_latency_ns``: Minimum processing latency (nano-seconds)
246 - ``avg_latency_ns``: Average processing latency (nano-seconds)
247 - ``mac_latency_ns``: Maximum processing latency (nano-seconds)
248 - ``jitter_ns``: Variance in processing latency (nano-seconds)
H A Dgraph_lib.rst7 Graph architecture abstracts the data processing functions as a ``node`` and
9 data processing functions.
23 - Inbuilt nodes for packet processing.
34 - Memory latency is the enemy for high-speed packet processing, moving the
35 similar packet processing code to a node will reduce the I cache and D
39 - Allow SIMD instructions for packet processing of the node.-
145 functions can links them together to create a complex packet processing graph.
193 Multicore graph processing
199 processing strategy would be to create graph object PER WORKER.
275 * Firstly, there has to be the best possible packet processing logic.
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H A Doverview.rst12 complete framework for fast packet processing in data plane applications.
27 The DPDK implements a run to completion model for packet processing,
29 running as execution units on logical processing cores.
31 …rimary reason for not using interrupts is the performance overhead imposed by interrupt processing.
88 for high-performance packet processing applications.
H A Dtraffic_metering_and_policing.rst35 Once successfully created, an MTR object is hooked into the RX processing path
41 Run-time processing
49 The processing done for each input packet hitting an MTR object is:
/f-stack/dpdk/doc/guides/sample_app_ug/
H A Dkeep_alive.rst8 heartbeat/watchdog for packet processing cores. It demonstrates how
19 on packet processing cores. A Keep Alive Monitor Agent Core (main)
20 monitors the state of packet processing cores (worker cores) by
25 callback function is invoked to restart the packet processing core;
124 addition to the main processing loop is the mark alive
H A Dvhost_crypto.rst45 instances of this config item is supported and one lcore supports processing
55 processing.
H A Dmulti_process.rst9 This chapter describes the example applications for multi-processing that are included in the DPDK.
142 with each process performing the same set of packet- processing operations.
144 we refer to this as symmetric multi-processing, to differentiate it from asymmetric multi- processi…
146 where different processes perform different tasks, yet co-operate to form a packet-processing syste…
171 … total number of symmetric_mp instances that will be run side-by-side to perform packet processing.
246 use a client-server type multi-process design to do packet processing.
249 which perform the actual packet processing.
/f-stack/freebsd/contrib/device-tree/Bindings/media/
H A Drenesas,vsp1.txt3 The VSP is a video processing engine that supports up-/down-scaling, alpha
4 blending, color space conversion and various other image processing features.
H A Drenesas,vsp1.yaml13 The VSP is a video processing engine that supports up-/down-scaling, alpha
14 blending, color space conversion and various other image processing features.
H A Dfsl-pxp.txt4 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
/f-stack/freebsd/contrib/device-tree/Bindings/input/touchscreen/
H A Dcyttsp.txt28 scanning/processing cycles when the chip is in active mode.
31 scanning/processing cycles when the chip is in low-power mode.
40 scanning/processing cycle).
/f-stack/dpdk/doc/guides/howto/
H A Ddebug_troubleshoot.rst7 DPDK applications can be designed to have simple or complex pipeline processing
34 primary process, with various processing stages running on multiple cores. The
191 Is there a variance in packet or object processing rate in the pipeline?
202 #. Stall in processing pipeline can be attributes of MBUF release delays.
205 * Heavy processing cycles at single or multiple processing stages.
222 #. Lower performance between the pipeline processing stages can be
231 * Try prefetching the content in processing pipeline logic to minimize the
407 Packet capture before and after processing :numref:`dtg_pdump`.
415 #. To isolate the possible packet corruption in the processing pipeline,
/f-stack/freebsd/contrib/device-tree/Bindings/arm/
H A Dmicrochip,sparx5.yaml17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
/f-stack/freebsd/contrib/device-tree/Bindings/display/bridge/
H A Dmegachips-stdpxxxx-ge-b850v3-fw.txt5 The video processing pipeline on the second output on the GE B850v3:
15 The hardware do not provide control over the video processing pipeline, as the
/f-stack/freebsd/contrib/device-tree/Bindings/sound/
H A Dnvidia,tegra210-ahub.yaml11 for audio pre-processing, post-processing and a programmable full
/f-stack/dpdk/
H A DREADME1 DPDK is a set of libraries and drivers for fast packet processing.
/f-stack/freebsd/contrib/device-tree/Bindings/mfd/
H A Dbrcm,iproc-mhb.txt5 interface; 3) access to the Nitro (network processing) engine
/f-stack/freebsd/contrib/device-tree/Bindings/misc/
H A Dxlnx,sd-fec.txt14 - "core_clk", Main processing clock for processing core (required)
/f-stack/freebsd/contrib/device-tree/Bindings/soc/xilinx/
H A Dxlnx,vcu.txt7 LogicoreIP design to provide the isolation between processing system

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