Searched refs:n_width (Results 1 – 2 of 2) sorted by relevance
| /f-stack/freebsd/arm/nvidia/tegra124/ |
| H A D | tegra124_clk_pll.c | 100 uint32_t n_width; member
498 *n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in get_divisors()
510 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in set_divisors()
702 if (n >= (1 << mnp_bits->n_width)) in pll_set_std()
725 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pll_set_std()
824 if (n >= (1 << mnp_bits->n_width)) in plld2_set_freq()
891 if (n >= (1 << mnp_bits->n_width)) in pllx_set_freq()
912 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pllx_set_freq()
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| /f-stack/freebsd/arm64/nvidia/tegra210/ |
| H A D | tegra210_clk_pll.c | 125 uint32_t n_width; member
691 *n = get_masked(val, mnp_bits->n_shift, mnp_bits->n_width); in get_divisors()
703 val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width); in set_divisors()
900 if (n >= (1 << mnp_bits->n_width)) in pll_set_std()
923 reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width); in pll_set_std()
1047 if (n >= (1 << mnp_bits->n_width)) in plld2_set_freq()
1129 if (n >= (1 << mnp_bits->n_width)) in pllx_set_freq()
1183 mnp_bits->n_width); in pllx_set_freq()
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