Searched refs:mask_bits (Results 1 – 2 of 2) sorted by relevance
96 u32 mask_bits = desc->masked; in igbuio_msix_mask_irq() local101 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; in igbuio_msix_mask_irq()103 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; in igbuio_msix_mask_irq()105 if (mask_bits != desc->masked) { in igbuio_msix_mask_irq()106 writel(mask_bits, desc->mask_base + offset); in igbuio_msix_mask_irq()108 desc->masked = mask_bits; in igbuio_msix_mask_irq()118 u32 mask_bits = desc->masked; in igbuio_msi_mask_irq() local126 mask_bits &= ~mask; in igbuio_msi_mask_irq()128 mask_bits |= mask; in igbuio_msi_mask_irq()130 if (mask_bits != desc->masked) { in igbuio_msi_mask_irq()[all …]
278 u32 mask_bits; in hinic_set_msix_state() local286 mask_bits = readl(hwif->intr_regs_base + offset); in hinic_set_msix_state()287 mask_bits &= ~HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; in hinic_set_msix_state()289 mask_bits |= HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; in hinic_set_msix_state()291 writel(mask_bits, hwif->intr_regs_base + offset); in hinic_set_msix_state()