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Searched refs:div_reg (Results 1 – 4 of 4) sorted by relevance

/f-stack/freebsd/mips/ingenic/
H A Djz4780_clk_gen.c168 div_reg = divider >> sc->clk_descr->clk_div.div_lg; in jz4780_clk_gen_set_freq()
169 divider = div_reg << sc->clk_descr->clk_div.div_lg; in jz4780_clk_gen_set_freq()
177 div_reg--; in jz4780_clk_gen_set_freq()
179 div_reg++; in jz4780_clk_gen_set_freq()
180 if (div_reg == 0) in jz4780_clk_gen_set_freq()
181 div_reg = 1; in jz4780_clk_gen_set_freq()
186 if (div_reg > div_msk + 1) { in jz4780_clk_gen_set_freq()
188 div_reg = div_msk; in jz4780_clk_gen_set_freq()
192 div_reg--; in jz4780_clk_gen_set_freq()
204 reg = CLK_RD_4(sc, sc->clk_descr->clk_div.div_reg); in jz4780_clk_gen_set_freq()
[all …]
H A Djz4780_clk.h57 uint16_t div_reg; member
H A Djz4780_clock.c111 .clk_div.div_reg = (reg), \
/f-stack/freebsd/arm64/rockchip/clk/
H A Drk_clk_composite.c230 uint32_t div, div_reg; in rk_clk_composite_find_best() local
236 for (div_reg = 0; div_reg <= ((sc->div_mask >> sc->div_shift) + 1); in rk_clk_composite_find_best()
237 div_reg++) { in rk_clk_composite_find_best()
239 div = 1 << div_reg; in rk_clk_composite_find_best()
241 div = div_reg + 1; in rk_clk_composite_find_best()
246 best_div_reg = div_reg; in rk_clk_composite_find_best()
250 *reg = div_reg; in rk_clk_composite_find_best()
262 uint32_t div, div_reg, best_div, best_div_reg, val; in rk_clk_composite_set_freq() local
274 div = rk_clk_composite_find_best(sc, fparent, *fout, &div_reg); in rk_clk_composite_set_freq()
279 best_div_reg = div_reg; in rk_clk_composite_set_freq()