Searched refs:div0 (Results 1 – 1 of 1) sorted by relevance
218 int div0, div1; in cgem_set_ref_clk() local227 div0 = (io_pll_frequency + div1 * frequency / 2) / in cgem_set_ref_clk()229 if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX && in cgem_set_ref_clk()319 int div0, div1; in zy7_pl_fclk_set_freq() local349 div0 = (base_frequency + div1 * frequency / 2) / in zy7_pl_fclk_set_freq()351 if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX && in zy7_pl_fclk_set_freq()378 return (base_frequency / div0 / div1); in zy7_pl_fclk_set_freq()385 int div0, div1; in zy7_pl_fclk_get_freq() local423 if (div0 == 0) in zy7_pl_fclk_get_freq()424 div0 = 1; in zy7_pl_fclk_get_freq()[all …]