| /f-stack/dpdk/drivers/raw/ifpga/base/ |
| H A D | ifpga_defines.h | 108 u64 csr; member
127 u64 csr; member
138 u64 csr; member
148 u64 csr; member
185 u64 csr; member
201 u64 csr; member
215 u64 csr; member
227 u64 csr; member
241 u64 csr; member
266 u64 csr; member
[all …]
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| H A D | ifpga_fme_error.c | 14 fme_error0.csr = readq(&fme_err->fme_err); in fme_err_get_errors()
15 *val = fme_error0.csr; in fme_err_get_errors()
68 header.csr = readq(&fme_err->header); in fme_err_get_revision()
81 pcie0_err.csr = readq(&fme_err->pcie0_err); in fme_err_get_pcie0_errors()
82 *val = pcie0_err.csr; in fme_err_get_pcie0_errors()
99 if (val != pcie0_err.csr) in fme_err_set_pcie0_errors()
119 *val = pcie1_err.csr; in fme_err_get_pcie1_errors()
136 if (val != pcie1_err.csr) in fme_err_set_pcie1_errors()
156 *val = ras_nonfaterr.csr; in fme_err_get_nonfatal_errors()
169 *val = ras_catfaterr.csr; in fme_err_get_catfatal_errors()
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| H A D | ifpga_feature_dev.c | 30 control.csr = readq(&port_hdr->control); in __fpga_port_enable()
32 writeq(control.csr, &port_hdr->control); in __fpga_port_enable()
48 control.csr = readq(&port_hdr->control); in __fpga_port_disable()
50 writeq(control.csr, &port_hdr->control); in __fpga_port_disable()
100 err_mask.csr = PORT_ERR_MASK; in port_err_mask()
102 err_mask.csr = 0; in port_err_mask()
135 status.csr = readq(&port_hdr->status); in port_err_clear()
150 mask.csr = readq(&port_err->port_error); in port_err_clear()
152 if (mask.csr == err) { in port_err_clear()
153 writeq(mask.csr, &port_err->port_error); in port_err_clear()
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| H A D | ifpga_fme_iperf.c | 29 header.csr = readq(&iperf->header); in fme_iperf_get_revision()
42 ctl.csr = readq(&iperf->ch_ctl); in fme_iperf_get_cache_freeze()
58 ctl.csr = readq(&iperf->ch_ctl); in fme_iperf_set_cache_freeze()
60 writeq(ctl.csr, &iperf->ch_ctl); in fme_iperf_set_cache_freeze()
81 ctl.csr = readq(&iperf->ch_ctl); in read_cache_counter()
84 writeq(ctl.csr, &iperf->ch_ctl); in read_cache_counter()
96 ctr0.csr = readq(&iperf->ch_ctr0); in read_cache_counter()
97 ctr1.csr = readq(&iperf->ch_ctr1); in read_cache_counter()
132 ctl.csr = readq(&iperf->vtd_ctl); in fme_iperf_get_vtd_freeze()
149 ctl.csr = readq(&iperf->vtd_ctl); in fme_iperf_set_vtd_freeze()
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| H A D | ifpga_fme_pr.c | 15 fme_pr_status.csr = readq(&fme_pr->ccip_fme_pr_status); in pr_err_handle()
48 fme_pr_ctl.csr = readq(&fme_pr->ccip_fme_pr_control); in fme_pr_write_init()
50 writeq(fme_pr_ctl.csr, &fme_pr->ccip_fme_pr_control); in fme_pr_write_init()
61 fme_pr_ctl.csr = readq(&fme_pr->ccip_fme_pr_control); in fme_pr_write_init()
63 writeq(fme_pr_ctl.csr, &fme_pr->ccip_fme_pr_control); in fme_pr_write_init()
99 fme_pr_ctl.csr = readq(&fme_pr->ccip_fme_pr_control); in fme_pr_write()
102 writeq(fme_pr_ctl.csr, &fme_pr->ccip_fme_pr_control); in fme_pr_write()
129 writeq(fme_pr_data.csr, in fme_pr_write()
160 fme_pr_ctl.csr = readq(&fme_pr->ccip_fme_pr_control); in fme_pr_write_complete()
254 fme_capability.csr = readq(&fme_hdr->capability); in fme_pr()
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| H A D | ifpga_fme.c | 67 (unsigned long long)fme_hdr->capability.csr); in fme_hdr_init()
85 header.csr = readq(&fme_hdr->header); in fme_hdr_get_revision()
97 fme_capability.csr = readq(&fme_hdr->capability); in fme_hdr_get_ports_num()
109 fme_capability.csr = readq(&fme_hdr->capability); in fme_hdr_get_cache_size()
219 tmp_threshold.csr = readq(&thermal->threshold); in fme_thermal_set_threshold1()
236 writeq(tmp_threshold.csr, &thermal->threshold); in fme_thermal_set_threshold1()
268 tmp_threshold.csr = readq(&thermal->threshold); in fme_thermal_set_threshold2()
399 header.csr = readq(&fme_thermal->header); in fme_thermal_get_revision()
501 pm_status.csr = readq(&fme_power->status); in fme_pwr_get_consumed()
619 pm_status.csr = readq(&fme_power->status); in fme_pwr_get_rtl()
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| H A D | ifpga_fme_dperf.c | 29 header.csr = readq(&dperf->header); in fme_dperf_get_revision()
42 ctl.csr = readq(&dperf->fab_ctl); in fabric_pobj_is_enabled()
66 ctl.csr = readq(&dperf->fab_ctl); in read_fabric_counter()
68 writeq(ctl.csr, &dperf->fab_ctl); in read_fabric_counter()
79 ctr.csr = readq(&dperf->fab_ctr); in read_fabric_counter()
138 ctl.csr = readq(&dperf->fab_ctl); in fme_dperf_set_fab_port_enable()
146 writeq(ctl.csr, &dperf->fab_ctl); in fme_dperf_set_fab_port_enable()
159 ctl.csr = readq(&dperf->fab_ctl); in fme_dperf_get_fab_freeze()
176 ctl.csr = readq(&dperf->fab_ctl); in fme_dperf_set_fab_freeze()
178 writeq(ctl.csr, &dperf->fab_ctl); in fme_dperf_set_fab_freeze()
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| H A D | ifpga_enumerate.c | 35 header.csr = readq(start); in feature_revision()
44 header.csr = readq(start); in feature_size()
54 header.csr = readq(start); in feature_id()
172 capability.csr = readq(&port_hdr->capability); in parse_feature_port_uafu()
211 header.csr = readq(&afu_hdr->csr); in parse_feature_afus()
382 header.csr = readq(hdr); in parse_feature_fiu()
399 fiu_header.csr = readq(&fiu_hdr->csr); in parse_feature_fiu()
493 header.csr = readq(hdr); in parse_feature_private()
513 header.csr = readq(hdr); in parse_feature()
548 header.csr = readq(hdr); in parse_feature_list()
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| H A D | ifpga_port.c | 59 header.csr = readq(&port_hdr->header); in port_get_revision()
74 capability.csr = readq(&port_hdr->capability); in port_get_portidx()
88 control.csr = readq(&port_hdr->control); in port_get_latency_tolerance()
103 status.csr = readq(&port_hdr->status); in port_get_ap1_event()
120 status.csr = readq(&port_hdr->status); in port_set_ap1_event()
122 writeq(status.csr, &port_hdr->status); in port_set_ap1_event()
137 status.csr = readq(&port_hdr->status); in port_get_ap2_event()
154 status.csr = readq(&port_hdr->status); in port_set_ap2_event()
156 writeq(status.csr, &port_hdr->status); in port_set_ap2_event()
171 status.csr = readq(&port_hdr->status); in port_get_power_state()
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| H A D | ifpga_port_error.c | 14 header.csr = readq(&port_err->header); in port_err_get_revision()
27 error.csr = readq(&port_err->port_error); in port_err_get_errors()
28 *val = error.csr; in port_err_get_errors()
40 first_error.csr = readq(&port_err->port_first_error); in port_err_get_first_error()
41 *val = first_error.csr; in port_err_get_first_error()
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| H A D | ifpga_compat.h | 44 value.csr = readq(_reg_addr); \
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| /f-stack/freebsd/contrib/octeon-sdk/ |
| H A D | cvmx-helper.h | 95 chcsr_type csr; \
97 csr.u64 = cvmx_read_csr(chcsr_csr); \
99 csr.u64 = (chcsr_init); \
100 csr.chcsr_chip.chcsr_fld = (chcsr_val); \
101 cvmx_write_csr((chcsr_csr), csr.u64); \
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| /f-stack/freebsd/contrib/device-tree/src/arm64/apm/ |
| H A D | apm-storm.dtsi | 188 csr-offset = <0x0>;
189 csr-mask = <0x2>;
226 csr-mask = <0xa>;
237 csr-mask = <0x3>;
248 csr-mask = <0x3>;
261 csr-mask = <0x00>;
275 csr-mask = <0x3a>;
289 csr-mask = <0x3a>;
302 csr-mask = <0x05>;
315 csr-mask = <0x05>;
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| H A D | apm-shadowcat.dtsi | 326 csr-offset = <0x0>;
327 csr-mask = <0x2>;
341 reg-names = "csr-reg";
350 reg-names = "csr-reg";
359 reg-names = "csr-reg";
361 csr-mask = <0x3>;
372 csr-mask = <0x3>;
382 csr-offset = <0xc>;
383 csr-mask = <0x10>;
395 csr-offset = <0x0>;
[all …]
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| /f-stack/freebsd/contrib/device-tree/Bindings/clock/ |
| H A D | xgene.txt | 40 may include "csr-reg" and/or "div-reg". If this property
42 only "csr-reg".
49 - csr-offset : Offset to the CSR reset register from the reset address base.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
96 reg-name = "csr-reg";
120 reg-names = "csr-reg", "div-reg";
121 csr-offset = <0x0>;
122 csr-mask = <0x200>;
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| /f-stack/freebsd/contrib/device-tree/Bindings/net/ |
| H A D | ipq806x-dwmac.txt | 15 - qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
16 qsgmii-csr registers.
28 qcom,qsgmii-csr = <&qsgmii_csr>;
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| /f-stack/freebsd/arm/ti/ |
| H A D | ti_sdma.c | 220 uint32_t csr; in ti_sdma_intr() local
239 csr = ti_sdma_read_4(sc, DMA4_CSR(ch)); in ti_sdma_intr()
240 if (csr == 0) { in ti_sdma_intr()
254 if (csr & DMA4_CSR_DROP) in ti_sdma_intr()
258 if (csr & DMA4_CSR_SECURE_ERR) in ti_sdma_intr()
261 if (csr & DMA4_CSR_MISALIGNED_ADRS_ERR) in ti_sdma_intr()
264 if (csr & DMA4_CSR_TRANS_ERR) { in ti_sdma_intr()
281 channel->callback(ch, csr, channel->callback_data); in ti_sdma_intr()
585 uint32_t csr; in ti_sdma_get_channel_status() local
600 csr = ti_sdma_read_4(sc, DMA4_CSR(ch)); in ti_sdma_get_channel_status()
[all …]
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| /f-stack/freebsd/contrib/device-tree/Bindings/arm/ |
| H A D | sirf.yaml | 10 - Binghua Duan <binghua.duan@csr.com>
11 - Barry Song <Baohua.Song@csr.com>
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| /f-stack/freebsd/contrib/device-tree/Bindings/pci/ |
| H A D | altera-pcie-msi.txt | 8 "csr": CSR registers
22 reg-names = "csr", "vector_slave";
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| H A D | xgene-pci.txt | 10 "csr": controller configuration registers.
37 reg-names = "csr", "cfg";
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| /f-stack/freebsd/contrib/device-tree/src/arm/ |
| H A D | bcm59056.dtsi | 49 csr_reg: csr {
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| /f-stack/freebsd/contrib/device-tree/Bindings/mfd/ |
| H A D | brcm,bcm59056.txt | 22 csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr,
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| /f-stack/dpdk/drivers/net/nfp/nfpcore/ |
| H A D | nfp_cpp_pcie_ops.c | 107 char *csr; member
260 bar->csr = nfp->cfg + in nfp_bar_write()
263 *(uint32_t *)(bar->csr) = newcfg; in nfp_bar_write()
331 bar->csr = nfp->cfg + in nfp_enable_bars()
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| /f-stack/freebsd/amd64/amd64/ |
| H A D | fpu.c | 81 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) argument
157 void ldmxcsr(u_int csr);
158 void stmxcsr(u_int *csr);
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| /f-stack/freebsd/contrib/device-tree/Bindings/dma/ |
| H A D | apm-xgene-dma.txt | 29 reg-names = "csr-reg";
|