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/f-stack/dpdk/examples/vm_power_manager/
H A Doob_monitor_x86.c33 apply_policy(int core) in apply_policy() argument
55 core); in apply_policy()
64 core); in apply_policy()
159 core); in add_core_to_monitor()
171 core); in add_core_to_monitor()
180 core); in add_core_to_monitor()
193 core); in add_core_to_monitor()
225 core); in remove_core_from_monitor()
234 core); in remove_core_from_monitor()
243 core); in remove_core_from_monitor()
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H A Doob_monitor_nop.c14 apply_policy(__rte_unused int core) in apply_policy() argument
20 add_core_to_monitor(__rte_unused int core) in add_core_to_monitor() argument
26 remove_core_from_monitor(__rte_unused int core) in remove_core_from_monitor() argument
/f-stack/app/nginx-1.16.1/auto/
H A Dsources8 CORE_INCS="src/core"
10 CORE_DEPS="src/core/nginx.h \
11 src/core/ngx_config.h \
12 src/core/ngx_core.h \
13 src/core/ngx_log.h \
15 src/core/ngx_array.h \
16 src/core/ngx_list.h \
17 src/core/ngx_hash.h \
18 src/core/ngx_buf.h \
25 src/core/ngx_crc.h \
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/f-stack/freebsd/mips/cavium/
H A Docteon_wdog.c81 int core; in octeon_wdog_nmi() local
83 core = cvmx_get_core_num(); in octeon_wdog_nmi()
132 int core; in octeon_wdog_watchdog_fn() local
138 CPU_FOREACH(core) in octeon_wdog_watchdog_fn()
144 CPU_FOREACH(core) in octeon_wdog_watchdog_fn()
175 csc->csc_core = core; in octeon_wdog_setup()
180 OCTEON_IRQ_WDOG0 + core, OCTEON_IRQ_WDOG0 + core, 1, RF_ACTIVE); in octeon_wdog_setup()
183 __func__, core); in octeon_wdog_setup()
193 "cpu%u", core); in octeon_wdog_setup()
234 int core, i; in octeon_wdog_attach() local
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/f-stack/freebsd/contrib/octeon-sdk/
H A Dcvmx-pow.c140 int core; in __cvmx_pow_capture_v1() local
153 for (core=0; core<num_cores; core++) in __cvmx_pow_capture_v1()
160 load_addr.sstatus.coreid = core; in __cvmx_pow_capture_v1()
220 int core; in __cvmx_pow_capture_v2() local
233 for (core=0; core<num_cores; core++) in __cvmx_pow_capture_v2()
240 load_addr.sstatus_cn68xx.coreid = core; in __cvmx_pow_capture_v2()
403 int core; in __cvmx_pow_display_v1() local
424 for (core=0; core<num_cores; core++) in __cvmx_pow_display_v1()
434 …__cvmx_pow_entry_mark_list(dump->sstatus[core][bit_cur].s_sstatus2.index, CVMX_POW_LIST_CORE + cor… in __cvmx_pow_display_v1()
574 int core; in __cvmx_pow_display_v2() local
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H A Dcvmx-debug.c232 return state.focus_core == core; in __cvmx_debug_in_focus()
239 trampoline += core; in cvmx_debug_install_handler()
298 int core; in cvmx_debug_init() local
318 core = cvmx_get_core_num(); in cvmx_debug_init()
359 state.focus_core = core; in cvmx_debug_init()
441 if (core < 10) in cvmx_debug_putcorepacket()
444 packet[7] = core + '0'; in cvmx_debug_putcorepacket()
446 else if (core < 20) in cvmx_debug_putcorepacket()
451 else if (core < 30) in cvmx_debug_putcorepacket()
632 uint64_t core; in cvmx_debug_process_packet() local
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H A Dcvmx-coremask.h119 int core) in cvmx_coremask_is_set_core() argument
123 n = core % CVMX_COREMASK_HLDRSZ; in cvmx_coremask_is_set_core()
124 i = core / CVMX_COREMASK_HLDRSZ; in cvmx_coremask_is_set_core()
137 int core) in cvmx_coremask_set_core() argument
141 n = core % CVMX_COREMASK_HLDRSZ; in cvmx_coremask_set_core()
142 i = core / CVMX_COREMASK_HLDRSZ; in cvmx_coremask_set_core()
156 int core) in cvmx_coremask_clear_core() argument
160 n = core % CVMX_COREMASK_HLDRSZ; in cvmx_coremask_clear_core()
161 i = core / CVMX_COREMASK_HLDRSZ; in cvmx_coremask_clear_core()
H A Dcvmx-interrupt.c385 int core = cvmx_get_core_num(); in __cvmx_interrupt_ciu() local
389 ciu_offset = core * 2; in __cvmx_interrupt_ciu()
463 int core = cvmx_get_core_num(); in __cvmx_interrupt_ciu_cn61xx() local
469 ciu_offset = core * 2 + 1; in __cvmx_interrupt_ciu_cn61xx()
504 int core = cvmx_get_core_num(); in __cvmx_interrupt_ciu2() local
566 cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core)); in __cvmx_interrupt_ciu2()
720 int core = cvmx_get_core_num(); in __cvmx_interrupt_ciu2_mask_unmask_irq() local
732 reg = CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(core); in __cvmx_interrupt_ciu2_mask_unmask_irq()
772 int core = cvmx_get_core_num(); in __cvmx_interrupt_ciu_mask_unmask_irq() local
778 ciu_offset = core * 2; in __cvmx_interrupt_ciu_mask_unmask_irq()
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/f-stack/freebsd/contrib/device-tree/Bindings/clock/
H A Dmvebu-core-clock.txt53 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
54 "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
55 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
56 "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
57 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
58 "marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
59 "marvell,dove-core-clock" - for Dove SoC core clocks
63 "marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
76 core_clk: core-clocks@d0214 {
77 compatible = "marvell,dove-core-clock";
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/f-stack/freebsd/contrib/device-tree/Bindings/interrupt-controller/
H A Dti,c64x+megamod-pic.txt6 The core interrupt controller provides 16 prioritized interrupts to the
7 C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
9 sources coming from outside the core.
13 - compatible: Should be "ti,c64x+core-pic";
18 Single cell specifying the core interrupt priority level (4-15) where
26 compatible = "ti,c64x+core-pic";
35 may be cascaded into the core interrupt controller. The megamodule PIC
36 has a total of 12 outputs cascading into the core interrupt controller.
37 One for each core interrupt priority level. In addition to the combined
41 considered to have the core interrupt controller as the parent.
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/f-stack/dpdk/examples/service_cores/
H A Dmain.c128 uint32_t core = i + core_off; in apply_profile() local
129 ret = rte_service_lcore_add(core); in apply_profile()
131 printf("core %d added ret %d\n", core, ret); in apply_profile()
133 ret = rte_service_lcore_start(core); in apply_profile()
135 printf("core %d start ret %d\n", core, ret); in apply_profile()
138 if (rte_service_map_lcore_set(s, core, in apply_profile()
140 printf("failed to map lcore %d\n", core); in apply_profile()
145 uint32_t core = i + core_off; in apply_profile() local
147 ret = rte_service_map_lcore_set(s, core, 0); in apply_profile()
153 ret = rte_service_lcore_stop(core); in apply_profile()
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/f-stack/freebsd/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool/
H A Dzpool_003_pos.ksh69 [[ -f core ]] && log_must rm -f core
79 log_must sysctl kern.corefile=core
87 [[ -f core ]] || log_fail "zpool did not dump core by request."
88 [[ -f core ]] && log_must rm -f core
/f-stack/freebsd/contrib/device-tree/Bindings/mips/loongson/
H A Ddevices.yaml5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 - const: loongson,loongson64c-4core-ls7a
26 - const: loongson,loongson64c-4core-rs780e
30 - const: loongson,loongson64c-8core-rs780e
34 - const: loongson,loongson64g-4core-ls7a
38 - const: loongson,loongson64v-4core-virtio
/f-stack/freebsd/contrib/device-tree/src/c6x/
H A Dtms320c6678.dtsi61 compatible = "ti,c64x+core-pic";
81 ti,core-mask = < 0x01 >;
87 ti,core-mask = < 0x02 >;
93 ti,core-mask = < 0x04 >;
99 ti,core-mask = < 0x08 >;
105 ti,core-mask = < 0x10 >;
111 ti,core-mask = < 0x20 >;
117 ti,core-mask = < 0x40 >;
123 ti,core-mask = < 0x80 >;
H A Dtms320c6472.dtsi51 compatible = "ti,c64x+core-pic";
71 ti,core-mask = < 0x01 >;
77 ti,core-mask = < 0x02 >;
83 ti,core-mask = < 0x04 >;
89 ti,core-mask = < 0x08 >;
95 ti,core-mask = < 0x10 >;
101 ti,core-mask = < 0x20 >;
/f-stack/dpdk/doc/guides/sample_app_ug/
H A Dpacket_ordering.rst15 * RX core (main core) receives traffic from the NIC ports and feeds Worker
18 * Worker (worker core) basically do some light work on the packet.
22 * TX Core (worker core) receives traffic from Worker cores through software queues,
50 The first CPU core in the core mask is the main core and would be assigned to
51 RX core, the last to TX core and the rest to Worker cores.
H A Dtest_pipeline.rst15 * Core A ("RX core") receives traffic from the NIC ports and feeds core B with traffic through SW…
17 * Core B ("Pipeline core") implements a single-table DPDK pipeline
19 Core B receives traffic from core A through software queues,
21 are hit by the input packets and feeds it to core C through another set of software queues.
23 * Core C ("TX core") receives traffic from core B through software queues and sends it to the NIC…
51 The first CPU core in the core mask is assigned for core A, the second for core B and the third for…
104 …| | At run time, core A is creating the f…
106 … | | core B to use for table …
127 …| | At run time, core A is creating the f…
128 … | key and storing it into the packet meta data for core |
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/f-stack/freebsd/contrib/device-tree/Bindings/arm/
H A Darm,integrator.yaml5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
16 "core tiles" and referred to in the device tree as "core modules".
34 peripherals to make use of the core module. See ARM DUI 0159B.
43 core-module@10000000:
46 a core module child node. They are always at physical address
51 - const: arm,core-module-integrator
84 - core-module@10000000
/f-stack/freebsd/contrib/device-tree/Bindings/phy/
H A Dintel,combo-phy.yaml5 $schema: http://devicetree.org/meta-schemas/core.yaml#
30 - description: ComboPhy core registers
31 - description: PCIe app core control registers
35 - const: core
44 - const: core
91 reg-names = "core", "app";
96 reset-names = "phy", "core", "iphy0", "iphy1";
/f-stack/dpdk/doc/guides/prog_guide/
H A Dservice_cores.rst8 performing work on DPDK lcores. Service core support is built into the EAL, and
14 running services). The power of the service core concept is that the mapping
23 For detailed information about the service core API, please refer to the docs.
38 Each registered service can be individually mapped to a service core, or set of
39 service cores. Enabling a service on a particular core means that the lcore in
40 question will run the service. Disabling that core on the service stops the
44 service core, and map N workloads to M number of service cores. Each service
45 lcore loops over the services that are enabled for that core, and invokes the
51 The service core library is capable of collecting runtime statistics like number
/f-stack/dpdk/app/test/
H A Dtest_stack_perf.c38 unsigned int core[2]; in get_two_hyperthreads() local
45 core[0] = rte_lcore_to_cpu_id(id[0]); in get_two_hyperthreads()
46 core[1] = rte_lcore_to_cpu_id(id[1]); in get_two_hyperthreads()
49 if ((core[0] == core[1]) && (socket[0] == socket[1])) { in get_two_hyperthreads()
64 unsigned int core[2]; in get_two_cores() local
71 core[0] = rte_lcore_to_cpu_id(id[0]); in get_two_cores()
72 core[1] = rte_lcore_to_cpu_id(id[1]); in get_two_cores()
75 if ((core[0] != core[1]) && (socket[0] == socket[1])) { in get_two_cores()
/f-stack/freebsd/contrib/device-tree/Bindings/media/
H A Dqcom,sdm845-venus.yaml6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
35 - const: core
57 - const: core
83 - const: core
135 clock-names = "core", "iface", "bus";
145 clock-names = "core", "bus";
153 clock-names = "core", "bus";
H A Dqcom,msm8996-venus.yaml6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
35 - const: core
58 - const: core
83 - const: core
135 clock-names = "core", "iface", "bus", "mbus";
162 clock-names = "core";
169 clock-names = "core";
/f-stack/freebsd/contrib/device-tree/Bindings/gpu/
H A Dvivante,gc.yaml5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 description: Vivante GPU core devices
27 - description: GPU core clock
36 enum: [ bus, core, shader, reg ]
66 clock-names = "bus", "core", "shader";
/f-stack/freebsd/contrib/device-tree/Bindings/usb/
H A Dgr-udc.txt3 The GRUSBDC USB Device Controller core is available in the GRLIB VHDL
4 IP core library.
6 Note: In the ordinary environment for the core, a Leon SPARC system,
24 each OUT endpoint of the core. Fewer entries overrides the default sizes
30 each IN endpoint of the core. Fewer entries overrides the default sizes
33 For further information look in the documentation for the GLIB IP core library:

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