| /f-stack/freebsd/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | l2cache.txt | 9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
15 "fsl,b4420-l2-cache-controller"
16 "fsl,b4860-l2-cache-controller"
19 "fsl,c293-l2-cache-controller"
30 "fsl,p1010-l2-cache-controller"
[all …]
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| /f-stack/freebsd/contrib/device-tree/src/arm/ |
| H A D | exynos5410-pinctrl.dtsi | 13 gpio-controller;
21 gpio-controller;
29 gpio-controller;
37 gpio-controller;
45 gpio-controller;
53 gpio-controller;
61 gpio-controller;
69 gpio-controller;
77 gpio-controller;
85 gpio-controller;
[all …]
|
| H A D | exynos5260-pinctrl.dtsi | 16 gpio-controller;
24 gpio-controller;
32 gpio-controller;
40 gpio-controller;
48 gpio-controller;
56 gpio-controller;
64 gpio-controller;
72 gpio-controller;
80 gpio-controller;
88 gpio-controller;
[all …]
|
| H A D | exynos5420-pinctrl.dtsi | 16 gpio-controller;
24 gpio-controller;
35 gpio-controller;
46 gpio-controller;
54 gpio-controller;
78 gpio-controller;
86 gpio-controller;
94 gpio-controller;
102 gpio-controller;
110 gpio-controller;
[all …]
|
| H A D | exynos5250-pinctrl.dtsi | 16 gpio-controller;
24 gpio-controller;
32 gpio-controller;
40 gpio-controller;
48 gpio-controller;
56 gpio-controller;
64 gpio-controller;
72 gpio-controller;
80 gpio-controller;
88 gpio-controller;
[all …]
|
| H A D | hi3620.dtsi | 214 gpio-controller;
228 gpio-controller;
243 gpio-controller;
258 gpio-controller;
273 gpio-controller;
288 gpio-controller;
303 gpio-controller;
318 gpio-controller;
333 gpio-controller;
348 gpio-controller;
[all …]
|
| /f-stack/freebsd/contrib/device-tree/src/arm64/exynos/ |
| H A D | exynos7-pinctrl.dtsi | 16 gpio-controller;
33 gpio-controller;
50 gpio-controller;
58 gpio-controller;
68 gpio-controller;
76 gpio-controller;
84 gpio-controller;
92 gpio-controller;
100 gpio-controller;
108 gpio-controller;
[all …]
|
| H A D | exynos5433-pinctrl.dtsi | 24 gpio-controller;
41 gpio-controller;
58 gpio-controller;
66 gpio-controller;
74 gpio-controller;
82 gpio-controller;
90 gpio-controller;
98 gpio-controller;
106 gpio-controller;
116 gpio-controller;
[all …]
|
| /f-stack/freebsd/contrib/device-tree/Bindings/clock/ |
| H A D | exynos5433-clock.txt | 39 L2 cache controller.
68 Input clocks for top clock controller:
77 Input clocks for mif clock controller:
201 cmu_top: clock-controller@10030000 {
216 cmu_cpif: clock-controller@10fc0000 {
225 cmu_mif: clock-controller@105b0000 {
275 cmu_g2d: clock-controller@12460000 {
315 cmu_aud: clock-controller@114c0000 {
352 cmu_g3d: clock-controller@14aa0000 {
408 cmu_mfc: clock-controller@15280000 {
[all …]
|
| /f-stack/freebsd/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-mxs.yaml | 7 title: Freescale MXS GPIO controller
14 The Freescale MXS GPIO controller is part of MXS PIN controller.
16 As the GPIO controller is embedded in the PIN controller and all the
50 interrupt-controller: true
58 gpio-controller: true
64 - interrupt-controller
67 - gpio-controller
91 gpio-controller;
101 gpio-controller;
111 gpio-controller;
[all …]
|
| H A D | 8xxx_gpio.txt | 12 controller, see bindings/interrupt-controller/interrupts.txt (the
17 the SoC's internal interrupt controller). See the interrupt controller
29 - gpio-controller: Marks the port as GPIO controller.
33 module as an IRQ controller.
36 this interrupt controller. The first cell
43 Example of gpio-controller nodes for a MPC8347 SoC:
45 gpio1: gpio-controller@c00 {
51 gpio-controller;
52 interrupt-controller;
56 gpio2: gpio-controller@d00 {
[all …]
|
| H A D | intel,ixp4xx-gpio.txt | 3 This GPIO controller is found in the Intel IXP4xx processors.
6 The interrupt portions of the GPIO controller is hierarchical:
9 main IXP4xx interrupt controller which has a 1:1 mapping for
15 The interrupt parent of this GPIO controller must be the
16 IXP4xx interrupt controller.
23 - gpio-controller : marks this as a GPIO controller
25 - interrupt-controller : marks this as an interrupt controller
27 interrupt-controller/interrupts.txt
34 gpio-controller;
36 interrupt-controller;
|
| H A D | gpio-thunderx.txt | 1 Cavium ThunderX/OCTEON-TX GPIO controller bindings
4 - reg: The controller bus address.
5 - gpio-controller: Marks the device node as a GPIO controller.
7 - First cell is the GPIO pin number relative to the controller.
12 - interrupt-controller: Marks the device node as an interrupt controller.
14 "interrupt-controller" is present.
15 - First cell is the GPIO pin number relative to the controller.
23 gpio-controller;
25 interrupt-controller;
|
| /f-stack/freebsd/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | mrvl,intc.txt | 1 * Marvell MMP Interrupt controller
10 of the whole interrupt controller. The "marvell,mmp3-intc" controller
14 interrupt controller.
19 - interrupt-controller : Identifies the node as an interrupt controller.
23 controller.
30 interrupt-controller;
39 interrupt-controller;
46 * Marvell Orion Interrupt controller
52 - interrupt-controller : Declare this node to be an interrupt controller.
58 intc: interrupt-controller {
[all …]
|
| H A D | fsl,ls-scfg-msi.txt | 1 * Freescale Layerscape SCFG PCIe MSI controller
6 Layerscape PCIe MSI controller block such as:
12 - msi-controller: indicates that this is a PCIe MSI controller node
13 - reg: physical base address of the controller and length of memory mapped.
14 - interrupts: an interrupt to the parent interrupt controller.
16 This interrupt controller hardware is a second level interrupt controller that
17 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
19 controller will be used.
21 MSI controller node
25 msi1: msi-controller@1571000 {
[all …]
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| H A D | brcm,bcm7120-l2-intc.txt | 1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
14 controller, in particular for UARTs
22 The typical hardware layout for this controller is represented below:
56 - interrupt-controller: identifies the node as an interrupt controller
60 node, valid values depend on the type of parent interrupt controller
79 irq0_intc: interrupt-controller@f0406800 {
[all …]
|
| H A D | sigma,smp8642-intc.txt | 1 Sigma Designs SMP86xx/SMP87xx secondary interrupt controller
7 - interrupt-controller: boolean
13 - interrupt-controller: boolean
19 interrupt-controller@6e000 {
24 interrupt-controller;
28 irq0: interrupt-controller@0 {
30 interrupt-controller;
35 irq1: interrupt-controller@100 {
37 interrupt-controller;
42 irq2: interrupt-controller@300 {
[all …]
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| H A D | marvell,odmi-controller.txt | 4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
26 See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
32 compatible = "marvell,ap806-odmi-controller",
33 "marvell,odmi-controller";
34 interrupt-controller;
35 msi-controller;
|
| /f-stack/freebsd/contrib/device-tree/Bindings/pci/ |
| H A D | pci-msi.txt | 38 * msi-controller is a single phandle to an MSI controller
66 msi: msi-controller@a {
69 msi-controller;
94 msi: msi-controller@a {
97 msi-controller;
123 msi: msi-controller@a {
126 msi-controller;
156 msi-controller;
186 msi-controller;
193 msi-controller;
[all …]
|
| H A D | aardvark-pci.txt | 1 Aardvark PCIe controller
3 This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
5 The Device Tree node describing an Aardvark PCIe controller must
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
16 - msi-controller: indicates that the PCIe controller can itself
18 - msi-parent: pointer to the MSI controller to be used
31 - interrupt-controller
45 msi-controller;
55 pcie_intc: interrupt-controller {
[all …]
|
| /f-stack/freebsd/contrib/device-tree/src/powerpc/ |
| H A D | mucmc52.dts | 13 &gpt0 { gpio-controller; };
163 gpio-controller;
169 gpio-controller;
175 gpio-controller;
181 gpio-controller;
187 gpio-controller;
193 gpio-controller;
199 gpio-controller;
205 gpio-controller;
211 gpio-controller;
[all …]
|
| /f-stack/freebsd/contrib/device-tree/Bindings/mux/ |
| H A D | mux-controller.txt | 1 Common multiplexer controller bindings
5 that uses the mux controller. Thus, a mux controller can possibly control
23 mux-ctrl-phandle : phandle to mux controller node
25 given mux controller (controller specific)
38 If the mux controller chip only provides a single mux controller, the
44 mux: mux-controller {
71 mux: mux-controller {
120 Mux controller nodes
134 mux controller chips with more than one mux controller, particularly when
136 state for a mux controller with a higher index.
[all …]
|
| /f-stack/freebsd/contrib/device-tree/Bindings/pinctrl/ |
| H A D | samsung-pinctrl.txt | 1 Samsung GPIO and Pin Mux/Config controller
41 wakeup-interrupt-controller {
51 - gpio-controller: identifies the node as a gpio controller and pin bank.
133 - interrupt-controller: identifies the controller node as interrupt-parent.
219 gpio-controller;
227 gpio-controller;
230 interrupt-controller;
238 gpio-controller;
241 interrupt-controller;
315 Example 2: A pin-controller node with external wakeup interrupt controller node.
[all …]
|
| /f-stack/freebsd/contrib/device-tree/Bindings/memory-controllers/fsl/ |
| H A D | ddr.txt | 1 Freescale DDR memory controller
5 - compatible : Should include "fsl,chip-memory-controller" where
7 "fsl,qoriq-memory-controller".
8 - reg : Address and size of DDR controller registers
9 - interrupts : Error interrupt of DDR controller
15 memory-controller@2000 {
16 compatible = "fsl,bsc9132-memory-controller";
24 ddr1: memory-controller@8000 {
25 compatible = "fsl,qoriq-memory-controller-v4.7",
26 "fsl,qoriq-memory-controller";
|
| /f-stack/freebsd/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | ath79-ddr-controller.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
3 The DDR controller of the AR7xxx and AR9xxx families provides an interface
10 - compatible: has to be "qca,<soc-type>-ddr-controller",
11 "qca,[ar7100|ar7240]-ddr-controller" as fallback.
12 On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
13 fallback, otherwise "qca,ar7240-ddr-controller" should be used.
14 - reg: Base address and size of the controller's memory area
20 ddr_ctrl: memory-controller@18000000 {
21 compatible = "qca,ar9132-ddr-controller",
22 "qca,ar7240-ddr-controller";
[all …]
|