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Searched refs:comp_mask (Results 1 – 14 of 14) sorted by relevance

/f-stack/dpdk/drivers/net/mlx5/linux/
H A Dmlx5_verbs.c208 .comp_mask = 0, in mlx5_rxq_ibv_cq_create()
211 .comp_mask = 0, in mlx5_rxq_ibv_cq_create()
214 cq_attr.mlx5.comp_mask |= in mlx5_rxq_ibv_cq_create()
303 .comp_mask = 0, in mlx5_rxq_ibv_wq_create()
543 .comp_mask = 0, in mlx5_ibv_ind_table_new()
592 qp_init_attr.comp_mask = in mlx5_ibv_hrxq_new()
599 qp_init_attr.comp_mask |= in mlx5_ibv_hrxq_new()
609 .comp_mask = in mlx5_ibv_hrxq_new()
630 .comp_mask = in mlx5_ibv_hrxq_new()
780 .comp_mask = 0, in mlx5_ibv_drop_action_create()
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H A Dmlx5_os.c126 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; in mlx5_os_get_dev_attr()
132 device_attr->comp_mask = dv_attr.comp_mask; in mlx5_os_get_dev_attr()
678 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; in mlx5_dev_spawn()
700 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; in mlx5_dev_spawn()
819 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; in mlx5_dev_spawn()
826 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; in mlx5_dev_spawn()
829 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; in mlx5_dev_spawn()
845 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) in mlx5_dev_spawn()
963 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | in mlx5_dev_spawn()
972 devx_port.comp_mask = 0; in mlx5_dev_spawn()
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H A Dmlx5_ethdev_os.c298 values.comp_mask = IBV_VALUES_MASK_RAW_CLOCK; in mlx5_read_clock()
/f-stack/dpdk/drivers/net/mlx5/
H A Dmlx5_rxtx_vec_sse.h594 __m128i comp_mask; in rxq_cq_process_v() local
707 comp_mask = _mm_and_si128(op_own, format_check); in rxq_cq_process_v()
708 comp_mask = _mm_cmpeq_epi32(comp_mask, format_check); in rxq_cq_process_v()
709 comp_mask = _mm_packs_epi32(comp_mask, zero); in rxq_cq_process_v()
711 comp_mask = _mm_andnot_si128(invalid_mask, comp_mask); in rxq_cq_process_v()
712 comp_idx = _mm_cvtsi128_si64(comp_mask); in rxq_cq_process_v()
H A Dmlx5_rxtx_vec_neon.h619 uint16x4_t comp_mask; in rxq_cq_process_v() local
758 comp_mask = vand_u16(op_own, format_check); in rxq_cq_process_v()
759 comp_mask = vceq_u16(comp_mask, format_check); in rxq_cq_process_v()
765 comp_mask = vbic_u16(comp_mask, invalid_mask); in rxq_cq_process_v()
768 comp_mask), 0)) / in rxq_cq_process_v()
H A Dmlx5_rxtx_vec_altivec.h869 vector unsigned char comp_mask; in rxq_cq_process_v() local
1122 comp_mask = (vector unsigned char) in rxq_cq_process_v()
1125 comp_mask = (vector unsigned char) in rxq_cq_process_v()
1126 vec_cmpeq((vector unsigned int)comp_mask, in rxq_cq_process_v()
1128 comp_mask = (vector unsigned char) in rxq_cq_process_v()
1129 vec_packs((vector unsigned int)comp_mask, in rxq_cq_process_v()
1133 comp_mask = (vector unsigned char) in rxq_cq_process_v()
1134 vec_andc((vector unsigned long)comp_mask, in rxq_cq_process_v()
1136 comp_idx = ((vector unsigned long)comp_mask)[0]; in rxq_cq_process_v()
H A Dmlx5.h91 uint64_t comp_mask; member
/f-stack/dpdk/drivers/net/mlx4/
H A Dmlx4_rxq.c212 .comp_mask = 0, in mlx4_rss_attach()
222 .comp_mask = (IBV_QP_INIT_ATTR_PD | in mlx4_rss_attach()
504 struct mlx4dv_cq dv_cq = { .comp_mask = MLX4DV_CQ_MASK_UAR, }; in mlx4_rxq_attach()
509 uint32_t comp_mask = 0; in mlx4_rxq_attach() local
527 comp_mask |= IBV_WQ_INIT_ATTR_FLAGS; in mlx4_rxq_attach()
537 .comp_mask = comp_mask, in mlx4_rxq_attach()
H A Dmlx4_txq.c450 .comp_mask = MLX4DV_QP_MASK_UAR_MMAP_OFFSET, in mlx4_tx_queue_setup()
465 if (!(dv_qp.comp_mask & MLX4DV_QP_MASK_UAR_MMAP_OFFSET)) { in mlx4_tx_queue_setup()
H A Dmlx4.c655 .comp_mask = 0, in mlx4_hw_rss_sup()
660 .comp_mask = in mlx4_hw_rss_sup()
/f-stack/dpdk/drivers/common/mlx5/linux/
H A Dmeson.build66 'struct ibv_counters_init_attr', 'comp_mask' ],
H A Dmlx5_glue.h127 uint64_t comp_mask; }; member
/f-stack/freebsd/contrib/alpine-hal/eth/
H A Dal_hal_eth_ec_regs.h176 uint32_t comp_mask; member
H A Dal_hal_eth_main.c390 al_reg_write32(&adapter->ec_regs_base->epe_p[idx].comp_mask, reg_entry->mask); in al_eth_epe_entry_set()