Searched refs:al_assert (Results 1 – 12 of 12) sorted by relevance
55 al_assert(regs_base); in al_iofic_config()73 al_assert(regs_base); in al_iofic_moder_res_config()95 al_assert(regs_base); in al_iofic_legacy_moder_interval_config()118 al_assert(regs_base); in al_iofic_msix_moder_interval_config()140 al_assert(regs_base); in al_iofic_msix_tgtid_attributes_config()163 al_assert(regs_base); in al_iofic_unmask_offset_get()177 al_assert(regs_base); in al_iofic_unmask()195 al_assert(regs_base); in al_iofic_mask()210 al_assert(regs_base); in al_iofic_read_mask()223 al_assert(regs_base); in al_iofic_read_cause()[all …]
237 al_assert(udma); in al_udma_init()279 al_assert(udma); in al_udma_q_init()280 al_assert(q_params); in al_udma_q_init()378 al_assert(udma_q); in al_udma_q_reset()444 al_assert(udma); in al_udma_q_handle_get()445 al_assert(q_handle); in al_udma_q_handle_get()462 al_assert(udma != NULL); in al_udma_state_set()525 al_assert(comp_ctrl != UDMA_STATE_RESERVED); in al_udma_state_get()526 al_assert(stream_if != UDMA_STATE_RESERVED); in al_udma_state_get()527 al_assert(data_rd != UDMA_STATE_RESERVED); in al_udma_state_get()[all …]
441 al_assert(udma_q); in al_udma_desc_get()466 al_assert(udma_q); in al_udma_ring_id_get()492 al_assert(udma_q); in al_udma_desc_action_add()493 al_assert((num > 0) && (num <= udma_q->size)); in al_udma_desc_action_add()526 al_assert(udma_q); in al_cdesc_next()527 al_assert(cdesc); in al_cdesc_next()630 al_assert(udma_q); in al_udma_cdesc_get_all()656 al_assert(udma_q); in al_udma_cdesc_ack()
573 al_assert(al_udma_iofic_level_and_group_valid(level, group)); in al_udma_iofic_unmask()593 al_assert(al_udma_iofic_level_and_group_valid(level, group)); in al_udma_iofic_mask()609 al_assert(al_udma_iofic_level_and_group_valid(level, group)); in al_udma_iofic_read_cause()627 al_assert(al_udma_iofic_level_and_group_valid(level, group)); in al_udma_iofic_clear_cause()
455 al_assert(0); in al_pcie_ib_hcrd_os_ob_reads_config_default()799 al_assert(0); in al_pcie_port_pf_params_config()825 al_assert(0); in al_pcie_port_pf_params_config()891 al_assert(0); in al_pcie_port_sris_config()1468 al_assert( in al_pcie_port_ib_hcrd_os_ob_reads_config()1486 al_assert( in al_pcie_port_ib_hcrd_os_ob_reads_config()1694 al_assert(params); in al_pcie_port_config()1880 al_assert(params); in al_pcie_pf_config()1991 al_assert(status); in al_pcie_link_status()2903 al_assert(hdr); in al_pcie_aer_err_tlp_hdr_get()[all …]
162 al_assert(obj); in al_serdes_reg_read()163 al_assert(data); in al_serdes_reg_read()203 al_assert(obj); in al_serdes_reg_write()279 al_assert(0); in al_serdes_bist_overrides_enable()485 al_assert(0); in al_serdes_group_pm_set()617 al_assert(0); in al_serdes_lane_pm_set()639 al_assert(0); in al_serdes_lane_pm_set()771 al_assert(0); in al_serdes_loopback_control()815 al_assert(0); in al_serdes_bist_pattern_select()1198 al_assert(obj); in al_serdes_eye_diag_sample()[all …]
78 al_assert(obj); in al_serdes_25g_reg_read()79 al_assert(data); in al_serdes_25g_reg_read()117 al_assert(obj); in al_serdes_25g_reg_write()387 al_assert(user_data); in al_serdes_25g_bist_pattern_select()402 al_assert(0); in al_serdes_25g_bist_pattern_select()578 al_assert(buf_size == (samples_left * sizeof(uint64_t))); in al_serdes_25g_eye_diag_run()626 al_assert(sample_width <= 40); in al_serdes_25g_eye_diag_run()1096 al_assert(data); in al_serdes_25g_gcfsm2_read()1214 al_assert(data); in al_serdes_25g_rx_leq_fsm_op()1215 al_assert(err); in al_serdes_25g_rx_leq_fsm_op()[all …]
306 al_assert(udma->type == UDMA_TX); in al_udma_m2s_packet_size_cfg_set()445 al_assert(max_descs <= AL_UDMA_M2S_MAX_ALLOWED_DESCS_PER_PACKET); in al_udma_m2s_max_descs_set()446 al_assert(max_descs > 0); in al_udma_m2s_max_descs_set()476 al_assert(max_descs <= AL_UDMA_S2M_MAX_ALLOWED_DESCS_PER_PACKET); in al_udma_s2m_max_descs_set()477 al_assert(max_descs > 0); in al_udma_s2m_max_descs_set()1126 al_assert(qid < DMA_MAX_Q); in al_udma_gen_tgtid_conf_queue_set()1173 al_assert(AL_FALSE); in al_udma_gen_tgtid_conf_queue_set()
147 al_assert(al_udma_iofic_level_and_group_valid(level, group)); in al_udma_iofic_unmask_offset_get()
351 #define al_assert(COND) \ macro
1646 al_assert(caps); in al_eth_capabilities_get()3588 al_assert(ts_index <= 7); in al_eth_tx_ts_val_get()3589 al_assert(ts_index >= 1); in al_eth_tx_ts_val_get()3964 al_assert(stats); in al_eth_mac_stats_get()4194 al_assert(stats); in al_eth_ec_stats_get()4243 al_assert(stats); in al_eth_ec_stat_udma_get()4470 al_assert(reg != 0); in al_eth_board_params_set()4686 al_assert(num_bytes <= 4); in al_eth_byte_arr_to_reg()4703 al_assert(wol->pswd != NULL); in al_eth_wol_enable()4713 al_assert(wol->ipv4 != NULL); in al_eth_wol_enable()[all …]
218 al_assert(lane == AL_ETH_AN__LT_LANE_0); in al_eth_an_lt_reg_read()656 al_assert(adapter); in al_eth_kr_an_validate_adv()753 al_assert(an_adv != NULL); in al_eth_kr_an_read_adv()