Searched refs:ZY7_SLCR_FPGA_CLK_CTRL (Results 1 – 2 of 2) sorted by relevance
276 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_set_source()279 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg); in zy7_pl_fclk_set_source()302 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_get_source()366 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_set_freq()371 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg); in zy7_pl_fclk_set_freq()415 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_get_freq()
152 #define ZY7_SLCR_FPGA_CLK_CTRL(unit) (0x0170 + 0x10 * (unit)) macro